• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.24-25
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• 2008

The effect of heat treatment in $HfO_2$ as charge trap with $SiO_2/Si_3N_4/SiO_2$ as tunnel oxide layer in capacitors has been investigated. Rapid thermal annealing (RTA) were carried out at the temperature range of 600 - $900^{\circ}C$. It is found that all devices carried out heat treatment have large threshold voltage shift Especially, device performed heat treatment at $900^{\circ}C$ has been confirmed the largest memory window. Also, Threshold voltage shift of device used conventional $SiO_2$ as tunnel oxide layer was smaller than that with $SiO_2/Si_3N_4/SiO_2$.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 하계학술대회 논문집 C
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• pp.1069-1071
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• 1995

The electrical properties of Al/TiN/Ti contact are investigated at submicron contacts. The contact resistance and contact leakage current are dependent on metallization, surface dopant concentration, semiconductor surface treatment and contact plug ion implantation. In this paper, the contact resistance and contact leakage current are studied according to surface dopant concentration, semiconductor surface treatment and contact plug ion implantation at 0.8 micron contact. The contact resistance and contact leakage current increases with increasing substrate ion concentration. HF cleaning represents high contact resistance but low contact leakage current while CDE cleaning represents low contact resistance but high contact leakage current. Contact plug ion implantation decreases contact resistance but increases contact leakage current. Specially, RTA represents good electrical properties.

• 한국세라믹학회지
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• 제33권9호
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• pp.1012-1018
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• 1996

To investigate the final structures and reactions of silicides a somewhat thick Ti monolayer Co monolayer and Co/Ti bilayer films were deposited on single Si(100) wafer by electron beam evaporation followed by heat treatment using RTA system in N2 ambient. TiO2 film formed between Ti and TiSi2 layers due to oxgen or moisture in the Ti monolayer sample. The final layer structure obtained after the silicidation heat-treatment of the Co/Ti bilayer sample turned out to be TiSi2/CoSi2/Ti-Co-Si alloy/CoSi2/Si sbustrate. This implies that imperfect layer inversion occurred due to the formation of Ti-Co-Si intermediate phase.

• 열처리공학회지
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• 제35권6호
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• pp.314-318
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• 2022

Transparent conducting ZnO/Ti/ZnO tri-layer films deposited on glass substrate with DC and RF magnetron sputtering were rapid thermal annealed at 150, 300 and 450℃ for 5 minutes and then effect of annealing temperature on the structural and optoelectronics properties of the films were investigated. The structural properties are strongly related to annealing temperature and the largest grain size is observed in the films annealed at 450℃. The electrical resistivity also decreases as low as 7.7 × 10^-4 Ωcm. The visible transmittance also depends on the annealing temperature. The films annealed at 450℃ show a higher transmittance of 80.6% in this study.

• 한국재료학회지
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• 제8권11호
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• pp.1048-1054
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• 1998

Pt 상부 전극 증착온도가 Pb(Zr,Ti)$O_3$(PZT) 박막의 전기적 특성에 미치는 영향에 대하여 연구하였다. Pt 상부 전극을 $200^{\circ}C$이상의 고온에서 증착하는 경우, Pt 전극의 하부에 위치한 PZT 박막은 강유전 특성이 심하게 저하되었으나, Pt 전극이 증착되지 않았던 부분은 강유전 특성이 저하되지 않았다. 이와 같은 현상이 발생된 것은 진공 chamber 내의 수증기가 Pt 상부전극의 촉매 작용에 의해 수소 원자로 분해되고, 이 분해된 수소 원자가 고온에서 Pt 하부의 PZT 박막 내로 확산해 들어가 PZT박막에 산소 공공을 만들어 내기 때문이다. Pt의 촉매 작용이 없이는 수증기의 수소 원자로의 분해가 어려우므로 Pt 전극이 덮여져 있지 않는 PZT 박막은 강유전 특성이 저하되지 않는다. 이러한 강유전 특성의 저하는 산소 분위기의 RTA(rapid thermal annealing)처리에 의해 회복이 되었다. 한편, 누설전류 특성은 Pt 상부 전극의 증착온도가 증가함에 따라 향상되는 특성을 보였다.

• 한국전기전자재료학회논문지
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• 제24권5호
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• pp.392-397
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• 2011

The effect of various post-annealing temperature to sputtered Pb(Zr,Ti)$O_3$ (PZT) thin films was investigated. The crystallization process, surface morphology and the electrical characteristics strongly depends on the rapid thermal annealing (RTA). In radio frequency (RF) sputtering methods, there were many papers mostly forcing on the crystal forming and the surface variations with different elements distribution (Pb, Ti, Zr, O) on the surface of the PZT layer. In this experiment, the post-annealing treatment promoted the Pb volatilization in PZT thin film and affected the Ti diffused throughout the Pt layer into the PZT layer. Second ion mass spectroscopy (SIMS) analysis was employed to show that the Pb element in the PZT layer was decreased at the same time the Ti element mass was slight decreased than Pb with increasing RTA temperature. That result prove the content of Pb affect the PZT thin film property.

• 한국재료학회지
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• 제8권12호
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• pp.1152-1157
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• 1998

금속 타겟들을 이용한 반응성 스퍼터링법으로 $460~540^{\circ}C$범위에서 $Pt/Ti/SiO_2$/Si 기판위에 PZT 박막을 증착하였다. Perovskite상의 핵형성을 위해 Pb 휘발이 적은 저온($480^{\circ}C$)에서 짧은 시간 동안 PZT 박막을 증착한 후 Pb가 PBT 박막내에 과잉으로 함유되는 것을 억제하기 위하여 증착 온도를 증가시켜 박막을 증착하는 2단계 증착법을 사용한 결과 54$0^{\circ}C$의 고온에서도 perovskite 단일상과 화학양론비에 가까운 조성을 얻을 수 있었다. 2단계 증착법으로 제조된 PZT 박막은 우수한 전기적 특성을 나타내었으며 후속 RTA 처리로 더욱 특성을 향상시킬 수 있었는데 $17\mu$C/$\textrm{cm}^2$의 잔류분극, 45kv/cm의 coercive field, 그러고 -500kv/cm의 높은 전기장에서도 $10^{-4}$ A/$\textrm{cm}^2$의 양호한 누설전류 특성을 나타내었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 춘계학술대회 논문집
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• pp.239-242
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• 1998

Ca $F_2$ films have superior gate insulator properties than conventional gate insulator such as $SiO_2$, Si $N_{x}$, $SiO_{x}$, and T $a_2$ $O_{5}$ to the side of lattice mismatch between Si substrate and interface trap charge density( $D_{it}$). Therefore, this material is enable to apply Thin Film Transistor(TFT) gate insulator. Most of gate oxide film have exhibited problems on high trap charge density, interface state in corporation with O-H bond created by mobile hydrogen and oxygen atom. This paper performed Ca $F_2$ property evaluation as MIM, MIS device fabrication. Ca $F_2$ films were deposited at the various substrate temperature using a thermal evaporation. Ca $F_2$ films was grown as polycrystalline film and showed grain size variation as a function of substrate temperature and RTA post-annealing treatment. C-V, I-V results exhibit almost low $D_{it}$(1.8$\times$10$^{11}$ $cm^{-1}$ /le $V^{-1}$ ) and higher $E_{br}$ (>0.87MV/cm) than reported that formerly. Structural analysis indicate that low $D_{it}$ and high $E_{br}$ were caused by low lattice mismatch(6%) and crystal growth direction. Ca $F_2$ as a gate insulator of TFT are presented in this paper paperaper

• 한국재료학회지
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• 제1권2호
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• pp.99-104
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• 1991

Ta-silicide의 게이트 전극 및 비트라인(bit line)으로의 사용가능성을 알아보기 위하여 As, P, $BF_2$가 $5{\times}10^15cm^-2$의 농도로 이온주입된 다결정 실리콘에 탄탈륨을 스퍼터링으로 증착한 후 급속 열처리로 Ta-silicide를 형성하였다. 형성된 Ta-silicide의 특성은 4-탐침법, X-rayghlwjf, SEM 단면사진과 ${\alpha}$-step으로 조사하였으며, 불순물들의 거동은 Secondary Ion Mass Spectroscopy(SIMS)로 알아보았다. $TaSi_2$의 형성은 $800^{\circ}C$에서 시작하며 $1000^{\circ}C$ 이상에서 완료됨을 알았다. 형성된 $TaSi_2$층으로 out-diffusion 하였다.

• Transactions on Electrical and Electronic Materials
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• 제6권2호
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• pp.51-56
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• 2005

Ferroelectric Bi$_{3.35}$Sm$_{0.65}$Ti$_{3}$O$_{12}$(BSmT) thin films were synthesized using a sol-gel process. Bi(TMHD)$_{3}$, Sm$_{5}$(O$^{i}$Pr)13, Ti(O$^{i}$Pr)4 were used as the precursors, which were dissolved in 2­methoxyethanol. The BSmT thin films were deposited on Pt/TiO$_{x}$/SiO$_{2}$/Si substrates by spin­coating. The electrical properties of the thin films were enhanced using rapid thermal annealing process (RTA) at 600 $^{circ}$C for 1 min in O$_{2}$. Thereafter, the thin films were annealed from 600 to 720 $^{circ}$C in oxygen ambient for 1 hr, which was followed by post-annealed for 1 hr after depositing a Pt electrode to enhance the electrical properties. X-ray diffraction (XRD) and scanning electron microscopy (SEM) were used to analyze the crystallinity and surface morphology of layered perovskite phase, respectively. The remanent polarization value of the BSmT thin films annealed at 720 $^{circ}$C after the RTA treatment was 35.31 $\mu$C/cmz at an applied voltage of 5 V.