• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.9
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• pp.835-842
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• 2009

DVB-SSP is a new broadcasting system for hybrid satellite communications, which supports mobile handheld systems and fixed terrestrial systems. However, a critical factor must be considered in upper layer decoding which including erasure Reed-Solomon error correction combined with cyclic redundancy check. If there is only one bit error in an IP packet, the entire IP packet is considered as unreliable bytes, even if it contains correct bytes. IF, for example, there is one real byte error, in an If packet of 512 bytes, 511 correct bytes are erased from the frame. Therefore, this paper proposed two kinds of upper layer decoding methods; LLR-based decoding and hybrid decoding. By means of simulation we show that the performance of the proposed decoding algorithm is superior to that of the conventional one.

• 전자공학회논문지 IE
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• v.44 no.2
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• pp.14-20
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• 2007

This paper presents quaternary D flip-flop with advanced performance. Quaternary D flip-flop is composed of the components such as thermometer code output circuit, EX-OR gate, bias inverter, transmission gate and binary D flip-flop circuit. The designed circuit is simulated by HSPICE in $0.35{\mu}m$ one-poly six-metal CMOS process parameters with a single +3.3V supply voltage. In the simulations, sampling frequencies is measured around 100MHz. The PDP parameters and FOM we estimated to be 59.3fJ, 33.7 respectively.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.7
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• pp.90-97
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• 1989

In this paper, we have taken the formation of two-dimension codeword named doubly-encoded code using the Reed-Solomon code, C1(32, 28) with minimum distance 5 and C2(32, 26) with minimum distance 7 and we have had computer simulation of these error correcting processes using modeled R-DAT (Rotationary Digital Audio Tape). As the result, the error rate per symbol has been decreased about 0.05 and on these processes, the newly developed digital signal processing technology such as erro correction using Berlekamp-Massey algorithm in frequency domain have been proven.

• Journal of Advanced Navigation Technology
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• v.16 no.2
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• pp.190-196
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• 2012

In this paper, we propose an improved error correction code in order to improve the performance of digital modems for HF data communications and verify the performance of the proposed scheme. The proposed scheme employs outer Reed-Solomon codes concatenated with inner convolutional codes. Numerical results show that the proposed system significantly improves the bit error rate performance compared to the conventional PACTOR-III modems. Hence, the proposed system can improve the bandwidth efficiency of digital modems for HF data communications.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.1054-1057
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• 2015

Real time processing is important in the industrial field. In this paper, we implement for Modbus/RTU(Remote Terminal Unit) protocol using LabVIEW based on serial communication. In other to obtain the experimental data from torque sense and voltage/current meter, Modbus/RTU protocol is implemented by LabVIEW tool. Mechanical loss can be calculated by torque, RPM, voltage, and current. Source code consist of panel and block diagram. We confirmed these source code can be applied in industrial field.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.9
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• pp.1-8
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• 1999

In this paper, we propose and analyze a concatenated coding scheme for DS/CDMA systems in asynchronous channels. In the concatenated coding, bandwidth efficient $2^{2L-2}$-state ${\frac{L}{L+1}}$-rate 2-MTCM with biorthogonal signal constellation is used for the inner code, and $(2^{L-1},\;{\lceil}\frac{2^{L-1}}{L/2}{\rceil})$ RS code is use for the outer code. It is shown that we can get considerable performance gain over the uncoded system without sacrificing the data transmission rate. The proposed system can be used as a coding scheme for reliable and high speed integrated information services of mobile communication systems.

• Convergence Security Journal
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• v.19 no.1
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• pp.97-101
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• 2019

If the operating system's core file contains an Intel PT, the debugger can not only check the program state at the time of the crash, but can also reconfigure the control flow that caused the crash. We can also extend the execution trace scope to the entire system to debug kernel panics and other system hangs. The second-generation PT, the WinIPT library, includes an Intel PT driver with additional code to run process and core-specific traces through the IOCTL and registry mechanisms provided by Windows 10 (RS5). In other words, the PT trace information, which was limited access only by the first generation PT, can be executed by process and core by the IOCTL and registry mechanism provided by the operating system in the second generation PT. In this paper, we compare and describe methods for collecting, storing, decoding and detecting malicious codes of data packets in a window environment using 1/2 generation PT.

• Journal of the Korean Society of Systems Engineering
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• v.14 no.2
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• pp.73-82
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• 2018

In this work, a hardware based cryptographic module for the cyber security of nuclear power plant is developed using a system engineering approach. Nuclear power plants are isolated from the Internet, but as shown in the case of Iran, Man-in-the-middle attacks (MITM) could be a threat to the safety of the nuclear facilities. This FPGA-based module does not have an operating system and it provides protection as a firewall and mitigates the cyber threats. The encryption equipment consists of an encryption module, a decryption module, and interfaces for communication between modules and systems. The Advanced Encryption Standard (AES)-128, which is formally approved as top level by U.S. National Security Agency for cryptographic algorithms, is adopted. The development of the cyber security module is implemented in two main phases: reverse engineering and re-engineering. In the reverse engineering phase, the cyber security plan and system requirements are analyzed, and the AES algorithm is decomposed into functional units. In the re-engineering phase, we model the logical architecture using Vitech CORE9 software and simulate it with the Enhanced Functional Flow Block Diagram (EFFBD), which confirms the performance improvements of the hardware-based cryptographic module as compared to software based cryptography. Following this, the Hardware description language (HDL) code is developed and tested to verify the integrity of the code. Then, the developed code is implemented on the FPGA and connected to the personal computer through Recommended Standard (RS)-232 communication to perform validation of the developed component. For the future work, the developed FPGA based encryption equipment will be verified and validated in its expected operating environment by connecting it to the Advanced power reactor (APR)-1400 simulator.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.5
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• pp.15-20
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• 2012

In this paper, we show new method to find the error locations of received Reed-Solomon code word. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by very simplified square/$X^4$ calculating circuit, parallel processing and not using the very complex Divider. The Reed Solomon decoder using this new Chien Machine can be applicated for data protection of almost all digital communication and consumer electronic devices.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1991.11a
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• pp.191-193
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• 1991

This paper is described about the on-line, real-time quality information management system as the infrastructure of CIM, which we developed for the full automatic washing machine assembly line. This System is composed of Ethernet LAN, RS-485 Network, POP terminal, BAR CODE Scanner, PLC, ROBOT, measuring equipments and real-time processing software. We will run this system from next month regularly.