• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.4C
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• pp.365-373
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• 2003

In this paper, we design a versatle RS decoder which can decode RS codes of any block length n as well as any message length k, based on a modified Euclid's algorithm (MEA). This unique feature is favorable for a shortened RS code of any block length it eliminates the need to insert zeros before decoding a shortened RS code. Furthermore, the value of error correcting capability t can be changed in real time at every codeword block. Thus, when a return channel is available, the error correcting capability can be adaptiverly altered according to channel state. The decoder permits 4-step pipelined processing : (1) syndrome calculation (2) MEA block (3) error magnitude calculation (4) decoder failure check. Each step is designed to form a structure suitable for decoding a RS code with varying block length. A new architecture is proposed for a MEA block in step (2) and an architecture of outputting in reversed order is employed for a polynomial evaluation in step (3). To maintain to throughput rate with less circuitry, the MEA block uses not only a multiplexing and recursive technique but also an overclocking technique. The adaptive RS decoder over GF($2^8$) with the maximal error correcting capability of 10 has been designed in VHDL, and successfully synthesized in a FPGA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1575-1582
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• 1998

Reed-Solomon(RS) code which is especially effective against burst error is studied as a forward error correction technique in this ppaer. The circuits of RS encoder and decoder for ASIC implementation are designed and presented employing modified Euclid's algorithm. The functionalities of the designed circuits are verified though C programs which simulates the circuits over the various errors and erasures. The pipelined circuits using systolic arrays are designed for ASIC realization in VHDL, and verified through the logic simulations. Finally the circuit synthesis of RS encoder and decoder can be achieved.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.1
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• pp.34-40
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• 1999

Reed-Solomon(RS) codes have been employed to correct burst errors in applications such as CD-ROM, HDTV, ATM and digital VCRs. For the decoding RS codes, the Berlekamp-Massey algorithm, Euclidean algorithm and modified Euclidean algorithm(MEA) have been developed among which the MEA becomes the most popular decoding scheme. We propose an efficient recursive cell architecture suitable for the MEA. The advantages of the proposed scheme are twofold. First, The proposed architecture uses about 25% less clock cycles required in the MEA operation than[1]. Second, the number of recursive MEA cells can be reduced, when the number of clock cycles spent in the MEA operation is larger than code word length n. thereby buffer requirement for the received words can be reduced. For demonstration, the MEA circurity for (128,124) RS code have been described and the MEA operation is verified through VHDL.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.5
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• pp.861-868
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• 2001

In this paper, the performance of Reed Solomon(RS)/convolution리 concatenated codes and turbo code using semi random interleaver over the radio communication channel was analyzed. In the result, we proved that the performance of decoder was excellent as increase the interleaver size, constraint length, and iteration number. When turbo code using semi random interleaver and Hsiconvolutional concatenated codes was constant constraint length L=5, BER=10-4 , each value of $E_b/N_o$ was 4.5〔dB〕 and 2.95〔dB〕. Therefore, when the constraint length was constant, we proved that the performance of turbo code is superior to RS/Convolutional concatenated codes about 1.55〔dB〕 in the case of BER=10-4.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.187-187
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• 2004

In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF($2^8$) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.29-38
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• 2004

In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF(2$^{8}$ ) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

• Proceedings of the KAIS Fall Conference
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• 2010.05a
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• pp.507-510
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• 2010

OFDM(Orthogonal Frequency Division Multiplexing)은 하나의 데이터 열(data stream)을 낮은 데이터 전송률을 갖는 작은 데이터로 나누고, 이들을 부반송파(subcarrier)를 통해 동시에 전송한다. OFDM이 차세대 전송방식으로 채택된 이유는 주파수 선택적 페이딩(frequency selective fading)이나 협대역(narrow band)간 간섭에 받는 영향이 적어 고속 통신이 가능하기 때문이다. 본 논문에서는 RS 부호(Reed-Solomon Code)를 사용하여 OFDM에서 대용량 데이터를 전송할 때 발생하기 쉬운 연집 오류(burst error)를 정정하도록 하였다. 또한 채널 사이에 파일롯 심볼(pilot symbol)을 삽입하여 채널 추정을 통한 신호의 타이밍 오류도 고려하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.1960-1965
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• 1999

In this paper, we propose a new method of erased concatenated code with RS-convolutional code. In the method, we make use of erasure for undecoded information when we have some errors in RS decoding. For decoding with erasure, the method is processed inner decoding and outer decoding again. After the erasure decoding, if the decoding result is better than the previous one, then we use this result. If not, use the previous one. In this paper, we use concatenated RS(63,31)-convolutional(4.1/2) code. Simulation result is compared with calculation result for performance analysis. According to the result, the proposed method has better performance than the others without erasure such that 2dB when 0.5$\leq\rho\leq$1 and 4dB when $\rho\leq$0.3.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.9C
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• pp.855-862
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• 2009

The path key establishment phase in the wireless sensor network is vulnerable to Byzantine attack. Huang and Hedhi proposed a Byzantine resilient multi-key establishment scheme using a systematic RS code, which has shortcomings of exposing a part of message symbols and inefficient transmission. In this paper, we propose a new Byzantine resilient multi-path key establishment scheme in which direct message symbols are not exposed to an adversary and are more efficiently transmitted the RS-encoded symbols to the destination node. In the Proposed scheme, a non-systematic RS code is used to transmit a generated indirect secret key and each encoded symbol is relayed through available paths between two sensor nodes. If enough symbols are collected at the destination node, it is possible to reconstruct the secret message through RS decoding.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.1
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• pp.25-34
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• 2012

This paper presents a universal architecture for variable-length eight-parallel Reed-Solomon (RS) decoder for high-rate WPAN systems. The proposed architecture can support not only RS(255,239) code but various shortened RS codes. Moreover, variable-length architecture provides variable low latency for various shortened RS codes and the eight-parallel design also provides high data processing rate. Using 90-$nm$ CMOS standard cell technology, the proposed RS decoder has been synthesized and measured for performance. The proposed RS decoder can provide a maximum 19-$Gbps$ data rate at clock frequency 300 $MHz$.