• Proceedings of the KSR Conference
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• 2005.05a
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• pp.819-824
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• 2005

This paper describes the measurement result of leakage current flowing arresters connected in feeder lines to propose an optimal management method. Twenty seven arresters set in seven areas were analyzed on a regular basis for 4 months. The results showed that the RMS and the peak value of the total leakage currents for soundness arresters were a range of $200uA{\sim}00uA$. respectively. During the period of measurement, the magnitude of the leakage current didn't show conspicious changes and there were impossible places to analyze arrester's status due to including high THD rate in a feeder line, From the study, leakage current measurement has to be performed at a condition without running an electric train in the line, and the allowable RMS value of soundness arrester is bellow 600uA.

• Proceedings of the KIEE Conference
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• 2006.07a
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• pp.460-461
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• 2006

Computer Loads can be found in all of modern society. The switching mode power supplies used in personal computers are major sources of harmonic currents. Harmonic currents can cause lots of harmonic problems such as disruption in computer performance. A series resonant filter is very effective in harmonic reduction for personal computer loads. Voltage sags are short duration reductions in rms voltage. The main causes of voltage sags are faults, motor starting, and transformer energizing. Personal computers are another example of devices sensitive to voltage sags. A serious voltage sag at the terminals way lead mis-operation of the equipment. This paper presents an in depth analysis to evaluate the effect of harmonics reduction based on the IEC 61000-3-2 and the effect of voltage sag using ITI curve by applying a series resonant filter for personal computer loads.

• Progress in Superconductivity and Cryogenics
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• v.6 no.3
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• pp.50-55
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• 2004

We fabricated and tested a resistive type superconducting fault current limiter (SFCL) of three-phase 6.6 $kV_{rms}/200 A_{rms}$ rating based on YBCO thin films grown on sapphire substrates with a diameter of 4 inches, Short circuit tests were carried out at a accredited test facility for single line-to- ground faults, phase-to-phase faults and three-phase faults, Each phase of the SFCL was composed of 8${\times}$6 elements connected in series and parallel respectively. Each element was designed to have the rated voltage of 600 $V_{rms}$. A NiCr shunt resistor of 23 Ω was connected to each element for simultaneous quenches. Firstly, single phase-to-ground fault tests were carried out. The SFCL successfully developed the impedance in the circuit within 0.12 msec after fault and controlled the fault current of 10 $kA_{rms} below 816 A_{peak}$ at the first half cycle. In addition, in case of phase-to-phase fault and three- phase fault test. simultaneous quenches among the SFCLs of the phases successfully accomplished. In conclusion. the SFCL showed excellent performance of current limitation upon fault and stable operation regardless of the amplitude of fault currents.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.10
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• pp.7189-7195
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• 2015

The method of moments (MoM) is implemented to simulate scattering from a PEC (perfectly electric conductor) cylinder in the TE(transversw electric) EFIE (Electric Field Integral Equation) approach. The procedure expresses the singularity integral and the hypersingularity integral in terms of an analytic function and employs a singularity isolation process coupled with numerical technique along the discretized segment to evaluate the self terms. It is known that, in the MoM technique, the choice of base functions and test functions is very important for the accuracy and convergence of the numerical analysis. Thus, in this paper, three conditions, obtained from the combination of basis functions and test functions, are adopted to get the induced currents on the PEC surface. These currents are compared to the analytical one in the relative rms current error to get the condition that shows fast convergence rate. The fast order of convergence of the current error, 2.528, is obtained under the combination of pulse basis function/delta test function.

• Journal of Korean Society of Coastal and Ocean Engineers
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• v.15 no.2
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• pp.97-107
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• 2003

In order to evaluate the effect of dry-wet treatment on well developed tidal flats along the complex coastal line in the western part of Korean Peninsula, we adopted a finite element tidal hydrodynamic simulation model, ADCIRC incorporating newly suggested dry-wet option and applied it to Chonbuk coastal area and Keum river estuary. Model comparison with observed current data by RMS error in the Chonbuk area shows very good agreement within 1cm/sec of tidal velocity difference and 3％ of error to maximum tidal currents. However there is not seen any significant advantages in dry-wet treatment. For the tidal volume tests in the Keum river estuary, the differences are satisfied within 5％ nevertheless of dry-wet treatment but in a near cross section it marks over 20％. However both results are almost same in tidal residual tests. Thus it can be concluded that dry-wet option is not always necessary in the simulation of long-term dispersion analysis.

• Progress in Superconductivity and Cryogenics
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• v.10 no.1
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• pp.10-14
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• 2008

Differently from BSCCO tapes which are fabricated by powder-in-tube method, the coated conductors are made by the evaporation of YBCO on metal substrate. Due to this structural merit, although the coated conductors are generally used for large current transportation, they are expected to be favorable to the purpose of the fault current limitation as well. In this study, using YBCO coated conductor having copper stabilizer formed by plating technique(produced by Superpower Co.), we investigated the over-current characteristics of the coated conductor. The coated conductors had 85 A $I_c$ and 90 K $T_c$. The resistance of the conductor was 0.93 $m{\Omega}/cm$ at 300 K and 0.17 $m{\Omega}/cm$ at the temperature right above $T_c$. To the coated conductors, we applied the voltages of the range from 150 $V_{rms}$ to 230 $V_{rms}$ and measured the V-I curves using four probe method. From the results, we could analyze the electric behavior of the coated conductor in flux flow state. As the current exceed $I_c$, the currents were distributed into the superconductor and metal stabilizer. The amounts of the currents shared through both current paths were calculated under the assumption that the ,Joule heating was perfectly eliminated by $LN_2$ surrounding the conductor. Finally, the condition for the stable current flowing state which does not affect the conductor was established from the analysis on the over-current characteristics.

• Progress in Superconductivity and Cryogenics
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• v.9 no.3
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• pp.57-61
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• 2007

The current limiting characteristics of hybrid SFCL with additional power electronic devices was investigated in order to improve operation reliabilities. The hybrid SFCL developed consists of a superconducting trigger (S/T) part, a fast switch (F/S) module and a current limiting (C/L) part. Although hybrid SFCL had shown a excellent current limiting characteristics, this device was rather vulnerable to the residual arc currents which could exist during fast switch operation. This undesirable arc should be extinguished as quickly as possible in order to implement perfect fault current commutation. So, in order to eliminate the residual arcs between fast switch contacts, the power electronic devices (IGBT or GTO) were connected in series between the S/T part and the interrupter of the F/S module. According to the fault tests conducting with an input voltage of $270\;V_{rms}$ and a fault current of $5\;kA_{rms}$, The power electronic devices could perfectly remove the arc generated between the contacts of the interrupter within 4 ms after the fault occurred. From the test analysis, it was confirmed that the hybrid SFCL could enhance the operation reliability by adopting additional power electronic devices.

• Journal of Power Electronics
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• v.12 no.4
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• pp.528-537
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• 2012

This paper presents an interleaved resonant converter with a parallel-series transformer connection in order to achieve ripple current reduction at the output capacitor, zero voltage turn-on for the active switches, zero current turn-off for the rectifier diodes, less voltage stress on the rectifier diodes, and less current stress on the transformer primary windings. The primary windings of the two transformers are connected in parallel in order to share the input current and to reduce the root-mean-square (rms) current on the primary windings. The secondary windings of the two transformers are connected in series in order to ensure that the transformer primary currents are balanced. A full-wave diode rectifier is used at the output side to clamp the voltage stress of the rectifier diode at the output voltage. Two circuit modules are operated with the interleaved PWM scheme so that the input and output ripple currents are reduced. Based on the resonant behavior, all of the active switches are turned on under zero voltage switching (ZVS), and the rectifier diodes are turned off under zero current switching (ZCS) if the operating switching frequency is less than the series resonant frequency. Finally, experiments with a 1kW prototype are described to verify the effectiveness of the proposed converter.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.8
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• pp.36-41
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• 2006

Computer Loads can be found in all of modern society. The switching mode power supplies used in personal computers are major sources of harmonic currents. Harmonic currents can cause lots of harmonic problems such as disruption in computer performance. A series resonant filter is very effective in harmonic reduction for personal computer loads. Voltage sags are short duration reductions in rms voltage. The main causes of voltage sags at faults, motor starting, and transformer energizing. Personal computers are another example of devices sensitive to voltage sags. A serious voltage sag at the terminals way lead mis-operation of the equipment. This paper presents an in depth analysis to evaluate the effect of harmonics reduction based on the IEC 61000-3-2 and the effect of voltage sag using ITI curve by applying a series resonant filter for personal computer loads.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.12
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• pp.562-567
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• 2003

Lightning arresters are deteriorated by repetition of protective operation against overvoltages or impulse currents in environments of its use. If a deteriorated arrester is left in power lines, it can lead to an accident such as a line to ground fault even in a normal system. Therefore, it is necessary to eliminate the deteriorated arrester in advance by checking the soundness of arresters on a regular basis, and to ensure the reliability of power systems by preventing accidents. Various deterioration diagnostic techniques and devices are suggested, and most of which measure leakage current components as an indicator of arrester ageing. However, the techniques based on the magnitude of leakage current measure simply RMS or peak value of leakage current components and do not provide detailed information needed in the diagnosis. In this study, we found that the wave height distributions of the total leakage currents are remarkably changed or a new wave height are produced with the progress of arrester deterioration. To propose a new technique for the diagnosis, we designed a leakage current detection unit and an analysis program which can measure leakage current magnitudes and analyze wave height distributions. From the experimental results, we confirmed that the proposed technique by analyzing the wave height distribution can simply diagnose the mode of defects such as a partial damage and an existence of punctures in arresters as well as deterioration of arresters.