• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.397-400
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• 2009

This paper describes ASIC design of Multimedia application SoC platform based RISC processor with BTB(Branch Target Buffer). For performance enhancement of platform, we use a simple branch prediction scheme, BTB structure, that stores a target address for branch instruction to remove pipeline harzard. Also, the platform includes a number of peripheral such as VGA controller, AC97 controller, UART controller, SRAM interface and Debug interface. The platform is designed and verified on a Xilinx VERTEX-4 FPGA using a number of test programs for functional tests and timing constraints. Finally, the platform is implemented into a single ASIC chip which can be operated at 100MHz clock frequency using the Chartered 0.18um process. As a result of performance estimation, the proposed platform shows about 5~9% performance improvement in comparison with the previous SoC Platform.

• ETRI Journal
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• v.10 no.3
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• pp.9-23
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• 1988

반도체 기술의 급격한 발전으로 마이크로프로세서를 이용하여 수퍼미니급의 컴퓨터를 개발하는 것이 가능하게 되었다. 따라서 프로세서 칩 개발노력이 증대되었으며 컴퓨터 구조 또는 프로세서 구조에 관한 연구도 여러 곳에서 진행되고 있다. 우리나라의 경우 독자적인 명령어를 갖는 컴퓨터를 개발하겠다는 노력은 미미하였으며 외부로 발표된 것은 전무한 상태이다. 본 논문은 한국전자통신연구소에서 개발하고 있는 독자적인 명령어 세트를 가지는 RISC 형태의 32 비트 마이크로프로세서인 HARP의 구조설계에 관한 것으로서 기본구조 설계를 위하여 1980년대 이후에 개발된 RISC 프로세서들에 대한 사례연구를 하였으며, 이를 바탕으로 HARP의 명령어 및 데이터 형식, 레지스터의 구성, 48비트의 가상 어드레스 사용방법, load/store 및 분기 명령어에서 사용되는 어드레싱 모드 그리고 HARP에서 정의한 39개의 명령어들에 대해 기술한다.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.885-888
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• 2005

In this study, we designed an ARM9 compatible RISC microprocessor using VHDL. The microprocessor was designed to support Harvard architecture with separate instruction cache and data cache. The state machine was optimized for multi-cycle instructions. In addition, a data forwarding mechanism was adopted to reduce the stall cycles due to data hazards. Assembly programs were up-loaded into a ROM block for system-level simulation. Proper operation of the designed microprocessor was confirmed by investigating the contents of the internal registers as well as the RAM block. Futhermore, the simulation results clearly indicated that the operation speed of the processor designed in this study is enhanced by reducing the execution cycles required for multiplication related instructions.

• The Journal of the Korea institute of electronic communication sciences
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• v.2 no.3
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• pp.163-167
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• 2007

In this paper, to design 8 bit RISC Microprocessor, a method of Clock Gating to reduce electric power consumption is proposed. In order to examine the priority, the comparison results of between a 8 bit Microprocessor which is not considered Low Power consumption and which is considered Low Power consumption using a methods of Clock Gating are represented. Within the a few periods, the results of comparing with a Microprocessor not considered the utilization of Clock Gating shows that the reduction of dynamic dissipation is minimized up to 21.56%.

• Transactions on Electrical and Electronic Materials
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• v.13 no.6
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• pp.278-282
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• 2012

Photovoltaic systems have emerged to be one of the cleanest energy systems. Therefore, many large scale solar parks and PV farms have been built to prepare for the post fossil fuel ages. However, due to their large scale, to efficiently manage and operate PV systems, they need to be visually monitored within the range of infrared ray through the Internet. To satisfy this need, the efficient implementation of a high performance video compression standard is required. This paper therefore presents an implementation of H.264 motion estimation, which is one of the most data-intensive and complicated functions in H.264. To achieve this, this work implements vector instructions in hardware and incorporates them in a generic RISC processor architecture, thus increasing the processing speed while minimizing hardware and software design efforts. Extensive simulation results show that this proposed implementation can process motion estimations up to 13 times faster.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.281-284
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• 2008

This paper describes ASIC design of multimedia SoC Platform. The implemented Platform consists of 32-bit OpenRISC1200 Microprocessor, WISHBONE on-chip bus, VGA Controller, Debug Interface, SRAM Interface and UART. The 32-bit OpenRISC1200 processor has 5 stage pipeline and Harvard architecture with separated instruction/data bus. The VGA Controller can display RCB data on a CRT or LCD monitor. The Debug Interface supports a debugging function for the Platform. The SRAM Interface supports 18-bit address bus and 32-bit data bus. The UART provides RS232 protocol, which supports serial communication function. The Platform is design and verified on a Xilinx VERTEX-4 XC4VLX80 FPGA board. Test code is generated by a cross compiler' and JTAG utility software and gdb are used to download the test code to the FPGA board through parallel cable. Finally, the Platform is implemented into a single ASIC chip using Chatered 0.18um process and it can operate at 100MHz clock frequency.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.33 no.2
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• pp.165-173
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• 2023

In this paper, we propose an optimal implementation of lightweight block ciphers, SIMECK and SIMON counter operation mode, on a 32-bit RISC-V processor. Utilizing the characteristics of the CTR operating mode, we propose round function optimization that precomputes some values, single plaintext optimization and two plaintext parallel optimization. Since there are no previous research results on SIMECK and SIMON on RISC-V, we compared the performance of implementations with and without precomputation techniques for single plaintext optimization and two plaintext parallel optimization implementations. As a result, the implementations to which the precomputation technique was applied showed a performance improvement of 1% compared to the implementations to which precomputation was not applied.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37B no.9
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• pp.814-821
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• 2012

We propose a network processor called an OmniFlow processor capable of wire-speed flow management by a hardware-based flow admission control(FAC) in this paper. Because the OmniFlow processor can set up and release a wire-speed connection for flows, the update period of flows can be set to a short time, and only active flows can be effectively managed by terminating a flow that does not have a packet transmitted within this period. Therefore, the FAC can be used to provide a reliable transmission of UDP as well as TCP applications. This processor is fabricated in 65nm CMOS technology, and total gate count is 25 million. It has 40 Gb/s throughput performance in using the 32 RISC cores when maximum operating frequency is 555MHz.

• ETRI Journal
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• v.10 no.3
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• pp.49-61
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• 1988

HARP(High-performance Architecture for Risc-type Processor)는 한국전자통신연구소에서 정의한 고유모델의 RISC형 32비트 CPU이다. HACAM(HArp CAche and Mmu)은 HARP의 캐쉬 메모리 및 MMU(Memory Management Unit)를 custom IC로 구현한 VLSI 칩이다. 본 논문에서는 HACAM의 구조 설계에 대해 메모리 구조 및 메모리 관리 방식, 캐쉬 메모리 및 HACAM의 구성 등으로 나누어 설명하고 그 타당성을 논하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.24-38
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• 2009

In this paper, we implement processor debugger based on OCD(On-Chip Debugger). Implemented debugger consist of software debugger that supports a functionality of symbolic debugging, OCD integrated into target processor as a function of debugging, and Interface & Control block which interfaces software debugger and OCD at high speed rates. The debugger supports c/assembly level debugging using software debugger as OCD is integrated into target processor. After OCD block is interfaced with 32bit RISC processor core and then implemented with FPGA, the verification of On-Chip Debugging System is carried out through connecting OCD and Interface & Control block, and SW debugger.