• Journal of Advanced Navigation Technology
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• v.14 no.2
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• pp.233-238
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• 2010

In this paper, we applied the forward and backward error recovery techniques to a reduced instruction set computer (risc) processor to develop two fault-tolerant processors, namely, fetch redundant risc (FRR) processor and a redundancy execute risc (RER) processor. To evaluate the fault-tolerance capability of three target processors, we developed the base risc processor, FRR processor, and RER processor in SystemC hardware description language. We performed fault injection experiment using the three SystemC processor models and the SystemC-based simulation fault injection technique. From the experiments, for the 1-bit transient fault, the failure rate of the FRR, RER, and base risc processor were 1%, 2.8%, and 8.9%, respectively. For the 1-bit permanent fault, the failure rate of the FRR, RER, and base risc processor were 4.3%, 6.5%, and 41%, respectively. As a result, for 1-bit fault, we found that the FRR processor is more reliable among three processors.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10c
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• pp.676-678
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• 2003

최근에 2.5G나 3G 이동 단말 장치를 위한 프로세서로, 다양한 멀티미디어가 가미된 응용구현이 가능하도록 RISC 프로세서와 DSP를 포함하는 단일 칩 프로세서 기술이 등장하고 있다. 이에 따라 듀얼 프로세서 구조에서 비디오 인코딩/디코딩의 처리 속도를 향상시키기 위안 비디오의 인코더/디코더 구조를 제안한다. 기존의 연구에서는 비디오의 인코딩/디코딩의 전 과정을 DSP가 담당하도록 설계하였으나 많은 비트 연산이 필요한 부분에서는 RISC 칩보다 효율성이 낮게 된다. 이러한 문제점을 해결하기 위하여 본 논문에서는 비디오 신호 처리의 인코딩/디코딩을 구성하는 모듈들을 DSP와 RISC의 특성에 맞도록 분리해 수행시킴으로써 효율성을 높이고자 한다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.1
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• pp.239-245
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• 2019

RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation. In this paper, according to the emergence of RISC-V architecture, we describe the RISC-V processor instruction set constituted by arithmetic logic, memory, branch, control, status register, environment call and break point instructions. Using ModelSim and Quartus-II, 38 instructions of RISC-V has been successfully simulated and synthesized.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.31 no.3
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• pp.473-480
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• 2021

To achieve the high-speed implementation of post-quantum cryptography, primitive operations should be tailored to the architecture of the target processor. In this paper, we present the optimized implementation of multiplier operation on RISC-V processor for post-quantum cryptography. Particularly, the column-wise multiplication algorithm is optimized with the primitive instruction of RISC-V processor, which improved the performance of 256-bit and 512-bit multiplication by 19% and 8% than previous works, respectively. Lastly, we suggest the instruction extension for the high-speed multiplication on the RISC-V processor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12C
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• pp.1617-1622
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• 2004

MPEG/Audio decoder for mobile multimedia systems requires low power consumption. Implementations of AV decoder using a single RISC processor often need high power consumption owing to cash-miss in case of insufficient cash memory. In this paper, we present a MPEG/Audio decoder for mobile handset applications and implement it on a RISC processor embedding a minimized DSP accelerator. Audio decoding algorithm is splined into two parts; computation intensive and control intensive parts. Those parts we, respectively, allocated to DSP and RISC core, which are designed to run in parallel to increase the processing efficiency. The proposed system implements MP3 and AAC decoders at l7MHz and 24MHz clocks, which are reductions of 48% and 40% of complexities in comparison with implementations on a single RISC processor. The proposed method is adequate for mobile multimedia applications with insufficient cash memory.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1166-1174
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• 2004

In this paper, a design of RISC-based transmission wrapper processor for TCP/IP protocol stack is described. The processor consists of input and output buffer memory with dual bank structure, 32-bit RISC microprocessor core, DMA unit with on-the-fly checksum capability, and memory module. To handle the various modes of TCP/IP protocol, hardware-software codesign approach based on RISC processor is used rather than the conventional state machine design. To eliminate large delay time due to sequential executions of data transfer and checksum operation, DMA module which can execute the checksum operation along with data transfer operation is adopted. The designed processor exclusive of variable-size input/output buffer consists of about 23,700 gates and its maximum operating frequency is about 167MHz under 0.35${\mu}m$ CMOS technology.

• KIPS Transactions on Computer and Communication Systems
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• v.11 no.1
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• pp.1-8
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• 2022

RISC-V is an open-source instruction set architecture which has a simple base structure and can be extensible depending on the purpose. In this paper, we designed a small and low-power 32-bit RISC-V processor to establish the base for research on RISC-V embedded systems. We designed a 2-stage pipelined processor which supports RISC-V base integer instruction set except for FENCE and EBREAK instructions. The processor also supports privileged ISA for trap handling. It used 1895 LUTs and 1195 flip-flops, and consumed 0.001W on Xilinx Zynq-7000 FPGA when synthesized using Vivado Design Suite. GPIO, UART, and timer peripherals are additionally used to compose the system. We verified the operation of the processor on FPGA with FreeRTOS at 16MHz. We used Dhrystone and Coremark benchmarks to measure the performance of the processor. This study aims to provide a low-power, high-efficiency microprocessor for future extension.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.2
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• pp.1-13
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• 1999

As the complexity of DSP (Digital Signal Processing) applications increases, the need for new architectures supporting efficient high-level language compilers also grows. By combining several DSP processor specific features, such as single cycle MAC (Multiply-and-ACcumulate), direct memory access, automatic address generation, and hardware looping, with a RISC core having many general purpose registers and orthogonal instructions, a high-performance and compiler-friendly RISC-based DSP processors can be designed. In this study, we develop a code-converter that can exploit these DSP architectural features by post-processing compiler-generated assembly code, and evaluate the performance effects of each feature using seven DSP-kernel benchmarks and a QCELP vocoder program. Finally, we also compare the performances with several existing DSP processors, such as TMS320C3x, TMS320C54x, and TMS320C5x.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.5
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• pp.115-121
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• 2023

RISC-V is an open-source instruction set architecture, and anyone can freely design and implement a RISC-V microprocessor. This paper designes and simulates the RISC-V architecture, synthesizing it in FPGA and verifying it using logic analyzer (ILA). RISC-V core is written in SystemVerilog, which has efficient design and high reusability, and can be used in various application fields. The RISC-V core is implemented as hardware by synthesizing it on the Ultra96-V2 FPGA board using Vivado, and the accuracy and operation of the design are verified through Integrated Logic Analyzer(ILA). As a result of the experiment, it is confirmed that the designed RISC-V core performs the expected operation, and these results can contribute to the design and verification of RISC-V based systems.

• Proceedings of the Korea Information Processing Society Conference
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• 2021.11a
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• pp.217-220
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• 2021

ICISC'19에서 기존 CHAM과 동일한 구조와 규격을 갖지만, 라운드 수만 증가시킨 revised CHAM이 발표되었다. CHAM은 사물인터넷에서 사용되는 저사양 프로세서에서 효율적인 구현이 가능한 특징을 갖고 있다. AVR, ARM 프로세서 상에서의 CHAM 암호 알고리즘에 대한 최적 구현은 존재하지만, 아직 RISC-V 프로세서 상에서의 CHAM 구현은 존재하지 않는다. 따라서, 본 논문에서는 RISC-V 프로세서 상에서의 Revised CHAM 알고리즘을 최초로 구현을 제안한다. CHAM 라운드 함수의 내부 구조의 일부를 생략하여 최적 구현하였다. 그리고 홀수 라운드와 짝수 라운드를 모듈별로 구현하여 필요에 따라 모듈을 호출하여 손쉽게 사용할 수 있게 하였다. 결과적으로, RISC-V 상에서 제안 기법 적용하기 전보다 제안 기법 적용 후에 12%의 속도 향상을 달성하였다.