• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.7
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• pp.1015-1024
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• 1990

This paper proposes a program counter unit(PCU) on the pipelined architecture of RISC (Reduced Instruction Set Computer) type high performance processors, PCU is used for supplying instruction addresses to memory units(Instruction Cache) efficiently. A RISC processor's PCU has to compute the instruction address within required intervals continnously. So, using the method of self-generated incrementor, is more efficient than the conventional one's using ALU or private adder. The proposed PCU is designed to have the fast +4(Byte Address) operation incrementor that has no carry propagation delay. Design specifications are taken by analyzing the whole data path operation of target processor's default and exceptional mode instructions. CMOS and wired logic circuit technologic are used in PCU for the fast operation which has small layout area and power dissipation. The schematic capture and logic, timing simulation of proposed PCU are performed on Apollo W/S using Mentor Graphics CAD tooks.

• Proceedings of the Korea Information Processing Society Conference
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• 2023.05a
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• pp.126-128
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• 2023

본 논문에서는 2-bit RISC-V 프로세서 상에서의 경량 블록 암호인 SPECK의 CTR 운용 모드에 대한 최적 구현을 제안한다. RISC-V 상에서의 SPECK 단일 평문과 2개의 평문에 대한 최적화와 고정된 논스 값을 사용하는 CTR 운용모드의 특징을 활용하여 일부 값에 대해 사전 연산을 하는 라운드 함수 최적화를 제안한다. 결과적으로, 레퍼런스 대비 제안된 기법은 단일 평문과 2개의 평문에 대해 각각 5.76배 2.24배 성능 향상을 확인하였으며, 사전 연산 기법을 적용하지 않은 최적 구현 대비 사전 연산 기법을 적용하였을 때, 1% 성능 향상을 확인하였다.

• Proceedings of the Korean Nuclear Society Conference
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• 2004.05a
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• pp.230-230
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• 2004

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.333-336
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• 2002

This paper purpose design and implementation of system bus for the effective interconnection between peripheral device and 32-bit microprocessor. The designed system bus support general bus protocol. Also, it is optimized for 32-bit microprocessor. It is divided into two system. high performance system bus and Peripheral system bus.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.345-348
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• 1999

본 논문에서는 내장형 응용에 적합한 RISC 마이크로프로세서와 DSP 프로세서의 기능을 유기적으로 결합한 구조를 연구하고 이를 설계한다. 프로그램의 크기를 줄이기 위해 RISC 명령어는 16비트 명령어 집합을 설계하고 분기 명령어로 인한 손실을 줄이기 위해 한 개의 지연 슬롯을 갖고 있다. DSP 명령어는 32비트 길이를 갖고 한 명령어로 곱셈, 덧셈(뺄셈), 두 가지 데이터 이동을 할 수 있어서 한 사이클에 최대 네 가지 동작을 할 수 있다 파이프라인 단계는 IF, ID, EX, MA, WB/DSP의 다섯 단계로 구성된다. DSP 기능을 지원하기 위해 내부 루프 버퍼를 갖고 정수 실행부에서는 주소 발생을 위한 전용 하드웨어와 DSP 유닛에서는 곱셈 및 누적 기능을 지원하기 위한 17 × 17 비트 곱셈기가 내장된다. 제안된 구조의 설계는 Verilog-HDL을 이용하여 top-down 설계 방식으로 설계되었고 각 기능 검증을 마친 후 3.3V, 0.6㎛ CMOS triple metal single poly 공정을 이용하여 합성하고 레이아웃 하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.735-745
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• 2001

Processors require both intensive and extensive functional verification in their design phase due to their general purpose. The proposed random vector verification method for embedded control RISC cores meets this goal by contributing assistance for conventional methods. The proposed method proved its effectiveness during the design of CalmRISCTM-32 developed by Yonsei Univ. and Samsung. It adopts a cycle-accurate instruction level simulator as a reference model, runs simulation in both the reference and the target HDL and reports errors if any difference is found between them. Consequently, it successfully covers errors designers easily pass over and establishes other new error check points.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.123-130
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• 2004

This paper describes a multiplier architecture optimized for 32 bit RISC processor with 3-stage pipeline. The multiplier of ARM7, the target processor, is variably carried out on the execution stage of pipeline within 7 cycles. The included multiplier employs a modified Booth's algerian to produce 64 bit multiplication and addition product and it has 6 separate instructions. We analyzed several multiplication algorithm such as radix4-32${\times}$8, radix4-32${\times}$16 and radix8-32${\times}$32 to decide which multiplication architecture is most fit for a typical architecture of ARM7. VLSI area, cycle delay time and execution cycle number is the index of an efficient design and the final multiplier was designed on these indexes. To verify the operation of embedded multiplier, it was simulated with various audio algorithms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.65-75
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• 2011

As the technology of SoC design has been developed, the debugging is more and more important and users want a fast and reliable debugger. This paper deals with an implementation of the fast debugger which can reduce a debugging processing cycle by designing a modified JTAG suitable for a new RISC processor debugger. Designed JTAG is embedded to the OCD of Core-A and works with SW debugger. We confirmed the functions and reliability of the debugger. By comparing to the original JTAG system, the debugging processing cycle of the proposed JTAG is reduced at 8.5~72.2% by each debugging function. Further more, the gate count is reduced at 31.8%.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.289-292
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• 2008

This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of OpenRISC processor and a clock gating algorithm using ODC (Observability Don't Care) operation for a low-power processor. The branch prediction algorithm has a structure using BTB(Branch Target Buffer) and 4-way set associative cache has lower miss rate than direct-mapped cache. The clock gating algorithm reduces dynamic power consumption. As a result of estimation of performance and dynamic power, the performance of the OpenRISC processor using the proposed algorithm is improved about 8.9% and dynamic power of the processor using samsung $0.18{\mu}m$ technology library is reduced by 13.9%.

• The Journal of the Convergence on Culture Technology
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• v.5 no.1
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• pp.395-399
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• 2019

In order to support various parallel computing systems, it is necessary to extend LLVM IR to more efficiently support vector / matrix and to design LLVM IR to machine code as a new algorithm. As shown in the IR example, RISC instruction generation is naturally generated because the RISC instruction is basically composed of the RISC instruction, and the vector instruction is also not supported. There is a need for new IR structures, command generation algorithms and related extensions to support vector / matrix more robustly. To do this, it is important to map each instruction in the LLVM IR to the appropriate instruction in the target architecture (vector / matrix) (instruction selection algorithm). It is necessary to understand the meaning of LLVM IR command, to compare the meaning of each instruction of the target architecture with syntax, and to select the instruction that matches the pattern to make mapping efficient.