Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Efficient Verification Method with Random Vectors for Embedded Control RISC Cores

내장형 제어 RISC코어를 위한 효율적인 랜덤 벡터 기능 검증 방법

  • 양훈모 (연세대학교 전자전기공학과) ;
  • 곽승호 (연세대학교 전자전기공학과) ;
  • 이문기 (연세대학교 전자전기공학과)
  • Published : 2001.10.01
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Abstract

Processors require both intensive and extensive functional verification in their design phase due to their general purpose. The proposed random vector verification method for embedded control RISC cores meets this goal by contributing assistance for conventional methods. The proposed method proved its effectiveness during the design of CalmRISCTM-32 developed by Yonsei Univ. and Samsung. It adopts a cycle-accurate instruction level simulator as a reference model, runs simulation in both the reference and the target HDL and reports errors if any difference is found between them. Consequently, it successfully covers errors designers easily pass over and establishes other new error check points.

범용성이란 측면은 프로세서의 설계 과정 중 기능 검증의 중요도를 크게 부각시킨다. 따라서 본 논문은 기존 시뮬레이션 방법과 병행하여 기능 검증의 효율성을 높일 수 있는 효율적인 랜덤 벡터 기능 검증 방법을 제시한다. 본 기능 검증 방법은 내장형 제어 RISC 코어에 적합하며 실제 연세대학교와 삼성전자가 공동 개발한 32비트 프로세서인 CalmRISCTM-32의 코어 기능 검증에 적용하여 효율성을 확인한 바 있다. 본 기능 검증 방법은 클락 기반의 명령어 수준 시뮬레이터를 개발하여 이를 참조 모델로 삼고 랜덤 벡터로 이루어진 워크로드에 대해 HDL 시뮬레이션 결과와 비교함으로써 오류 검출을 수행하며 일반적인 테스트 벡터로써 발견하기 어려운 오류 유형을 보완하는 동시에 설계자에게 새로운 오류 유형의 기준을 제시하는 효과를 지닌다.

Keywords

References

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