• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.440-447
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• 2002

This paper considerated about exact flow volume calculation method from factors having an influence on measurement and introduced in anesthesia ventilator realized spirometry system. System used differential pressure sensing method with factors, that is temperature, pressure, gas density, humidity and mucus etc. System optimized for low power system for mobile system. System composed analog interface part, signal processing part, display part. Analog interface part have differential pressure flow sensor and defferential pressure sensor. Signal processing part have AVR processor for low power system display part use serial port (RS232, SPT). so it display at pc monitor or send to anesthesia ventilator. System is stable by linearizing 2th characteristics of flow-differential pressure, auto correction of sensor. Noise reduced by algorithm with analog filter and digital processing. Small, light, low power system is good at mobile system and applied to patient in emergency or mobile. and, System is useful at anesthesia ventilator by using flow sensor.

• Smart Structures and Systems
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• v.6 no.5_6
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• pp.731-748
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• 2010

Impact detection and health monitoring are very important tasks for civil infrastructures, such as bridges. Piezoceramic based transducers are widely researched for these tasks due to the piezoceramic material's inherent advantages of dual sensing and actuation ability, which enables the active sensing method for structural health monitoring with a network of piezoceramic transducers. Wireless sensor networks, which are easy for deployment, have great potential in health monitoring systems for large civil infrastructures to identify early-age damages. However, most commercial wireless sensor networks are general purpose and may not be optimized for a network of piezoceramic based transducers. Wireless networks of piezoceramic transducers for active sensing have special requirements, such as relatively high sampling rate (at a few-thousand Hz), incorporation of an amplifier for the piezoceramic element for actuation, and low energy consumption for actuation. In this paper, a wireless network is specially designed for piezoceramic transducers to implement impact detection and active sensing for structural health monitoring. A power efficient embedded system is designed to form the wireless sensor network that is capable of high sampling rate. A 32 bit RISC wireless microcontroller is chosen as the main processor. Detailed design of the hardware system and software system of the wireless sensor network is presented in this paper. To verify the functionality of the wireless sensor network, it is deployed on a two-story concrete frame with embedded piezoceramic transducers, and the active sensing property of piezoceramic material is used to detect the damage in the structure. Experimental results show that the wireless sensor network can effectively implement active sensing and impact detection with high sampling rate while maintaining low power consumption by performing offline data processing and minimizing wireless communication.

• 한국노년학
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• v.38 no.4
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• pp.945-962
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• 2018

This study was aimed to examine the association between resilience and mental health among individuals aged 65 and older. The number of the sample was 2,004 older people living in Chuncheon city. The dependent variables were measured with depression and mental well-being. Depression was measured by the Center for Epidemiological Studies-Depression(CES-D) 10 items. Mental well-being was measured by Korean version of the Mental Health Continuum-Short Form(K-MHC-SF). The independent variable, resilience, was measured with the Connor-Davidson Resilience Scale(CD-RISC). Adjusted for age, gender, region, education, living arrangement, religion, employment, income, and self-rated health, a logistic regression analysis result showed that resilience was negatively associated with depression among older adults. On the other hand, a multiple regression analysis result showed that resilience was positively associated with mental well-being among older adults. The study findings suggest that resilience can promote mental health in later life. Implications for older adults suffering from mental health problems are also discussed.

• Korean Journal of Psychosomatic Medicine
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• v.29 no.1
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• pp.58-66
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• 2021

Objectives : The purpose of this study is to compare the psychosocial characteristics of patients diagnosed with functional gastrointestinal disorder (FGID) by classifying them into irritable bowel syndrome (IBS), functional dyspepsia (FD), functional constipation (FC), functional heartburn (FH) groups, and overlap group (two or more functional diseases) and to examine the factors associated with the quality of life (QoL) of patients with FGID. Methods : A total of 144 patients who were diagnosed with FGID were selected as the subjects. The demographical factors were investigated; Korean-Beck Depression Inventory-II (K-BDI-II), Korean-Beck Anxiety Inventory (K-BAI), Korean version of Childhood Trauma Questionnaire (K-CTQ), Multi-dimensional Scale of Perceived Social Support (MSPSS), Korean Version of Connor-Davidson Resilience Scale (K-CD-RISC), and World Health Organization Quality of Life Assessment Instrument Brief Form (WHOQOL-BREF) were used to evaluate the psychosocial factors. Results : TThe overlap group had a significantly higher K-BDI-II score (F=11.09, p<0.001) and K-BAI score (F=8.93, p<0.001) compared to other groups. In childhood trauma, the IBS patients had a difference in emotional neglect (F=2.54, p=0.04) than the FD patients. The QoL of FGID patients had a negative correlation with depression (r=-0.196, p<0.01), anxiety (r=-0.235, p<0.01), and childhood trauma (r=-0.222, p<0.01), and a positive correlation with social support (r=0.512, p<0.01) and resilience (r=0.581, p<0.01). Conclusions : Overlap group had a higher level of depression and anxiety, and the IBS patient group had a higher level of emotional neglect than the FD patient group in terms of childhood trauma.

• Korean Journal of Psychosomatic Medicine
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• v.25 no.2
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• pp.193-199
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• 2017

Objectives : Insomnia may be one of the risk factor for suicidal ideation, but little is known about the mechanism by which sleep disturbances confer risk for suicide. The aim of this study was to investigate examine whether insomnia severity would be associated with resilience and suicidal ideation, and whether resilience would mediate the relationship between insomnia and suicidal ideation. Methods : A total of 432 community-dwelling adults(227 male, 205 female,) completed the self-report questionnaire that covered basic socio-demographic data. To assess the psychological variables, the following instruments were applied: Insomnia Severity Index(ISI), Korean Version of the Connor-Davidson Resilience Scale(K-CD-RISC), Beck Hopelessness Scale(BHOP) and Scale for Suicidal Ideation(SSI-Beck). People with an ISI score of 8 or higher were defined as insomnia. Results : Greater insomnia symptom severity was significantly associated with higher level of suicidal ideation and lower level of resilience, adjusting for hopelessness, age, sex, presence of family members living together, and household income. Additional analysis revealed that disturbance of sleep initiation and disturbance of sleep maintenance were significantly associated with suicidal ideation. Mediation analyses revealed that resilience significantly accounted for the relationship between insomnia symptom severity and suicidal ideation. Conclusions : These findings suggest that the evaluation and control of insomnia and resilience may be needed to reduce the risk of suicide.

• Environmental and Resource Economics Review
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• v.21 no.3
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• pp.743-776
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• 2012

This study utilizes the meta-analysis for the benefits transfer (MA-BT) approach to measure social costs the 7 target sites in the City and County of Honolulu. The estimated MA models (MA-1 and MA-1) were evaluated in terms of validity and reliability criteria. This study utilized a parametric t-test and a non-parametric sign rank test for checking validity. A transfer error measured by an absolute percentage difference was utilized to check reliability their similarity. The GIS was utilized for data collection in order to measure social costs for each target site. The results clearly demonstrated that social costs were substantially higher thant direct costs and varied market conditions and different methods used. In terms of validity and reliability criteria, MA models were preferred to the mean transfer value approach. MA-BT approach is desirable for measuring social costs for a project designed to measure social costs for these 7 proposed landfill sites with inaccessible data, on short time frames, and with little money. If researchers and planners have enough time and money, they can implement primary research. If not, the meta-analysis for the benefits transfer approach can be much better than no framework. The use of a GIS can help to identify secondary data within a specific radius of each target site.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.37-47
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• 2016

The practical constraints on the commercial FPGAs which contain dedicated wide function multiplexers in their slice structure are incorporated with one of the most advanced FPGA mapping algorithms based on the AIG (And-Inverter Graph), one of the best logic representations in academia. As the first step of the mapping process, cuts are enumerated as intermediate structures. And then, the cuts which can be mapped to the multiplexers are recognized. Without any increased complexity, the delay and area of multiplexers as well as LUTs are calculated after checking the requirements for the tree construction such as symmetry and depth limit against dynamically changing mapping of neighboring nodes. Besides, the root positions of multiplexer trees are identified from the RTL code, and annotated to the AIG as AOs (Auxiliary Outputs). A new AIG embedding the multiplexer tree structures which are intentionally synthesized by Shannon expansion at the AOs, is overlapped with the optimized AIG. The lossless synthesis technique which employs FRAIG (Functionally Reduced AIG) is applied to this approach. The proposed approach and techniques are validated by implementing and applying them to two RISC processor examples, which yielded 13~30% area reduction, and up to 32% delay reduction. The research will be extended to take into account the constraints on the dedicated hardware for carry chains.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.50-61
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• 2010

Nowadays, the SoC is watched by all over the world with interest. The design trend of the SoC is hardware and software co-design which includes the design of hardware structure in RTL level and the development of embedded software. Also the technology is toward deep-submicron and the observability of the SoC's internal state is not easy. Because of the above reasons, the SoC debug is very difficult and time-consuming. So we need a reliable debugger to find the bugs in the SoC and embedded software. In this paper, we developed a hardware debugger named OCD. It is based on IEEE 1140.1 JTAG standard. In order to verify the operation of OCD, it is integrated into the 32bit RISC processor - Core-A (Core-A is the unique embedded processor designed by Korea) and is tested by interconnecting with software debugger. When embedding the OCD in Core-A, there is 14.7% gate count overhead. We can modify the DCU which occupies 2% gate count in OCD to adapt with other processors as a debugger.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.431-441
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• 2003

This paper presents the design of 32 bit microprocessor for a sequence control using a field programmable gate array(FPGA). The microprocessor was designed by a VHDL with top down method, the program memory was separated from the data memory for high speed execution of sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32 bits. And the real time debug operation was implemented for easeful debugging the designed processor with a single step run, PC break point run, data memory break point run. Also in this designed microprocessor, pulse instructions, step controllers, master controllers, BM and BCD type arithmetic instructions, barrel shift instructions were implemented for sequence logic control. The FPGA was synthesized under a Xilinx's Foundation 4.2i Project Manager using a V600EHQ240 which contains 600,000 gates. Finally simulation and experiment were successfully performed respectively. For showing good performance, the designed microprocessor for the sequence logic control was compared with the H8S/2148 microprocessor which contained many bit instructions for sequence logic control. The designed processor for the sequence logic showed good performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.9
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• pp.22-30
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• 2011

Recently, the rising demand for intelligent video surveillance system leads to high-performance face recognition systems. The solution for low-resolution images acquired by a long-distance camera is required to overcome the distance limits of the existing face recognition systems. For that reason, this paper proposes a hardware design of an image resolution enhancement algorithm for real-time intelligent video surveillance systems. The algorithm is synthesizing a high-resolution face image from an input low-resolution image, with the help of a large collection of other high-resolution face images, called training set. When we checked the performance of the algorithm at 32bit RISC micro-processor, the entire operation took about 25 sec, which is inappropriate for real-time target applications. Based on the result, we implemented the hardware module and verified it using Xilinx Virtex-4 and ARM9-based embedded processor(S3C2440A). The designed hardware can complete the whole operation within 33 msec, so it can deal with 30 frames per second. We expect that the proposed hardware could be one of the solutions not only for real-time processing at the embedded environment, but also for an easy integration with existing face recognition system.