• Title/Summary/Keyword: RISC

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Efficient Video Signal Processing Method on Dual Processor of RISC and DSP (RISC와 DSP의 듀얼 프로세서에서의 효율적인 비디오 신호 처리 방법)

  • 김범호;마평수
    • Proceedings of the Korean Information Science Society Conference
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    • 2003.10c
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    • pp.676-678
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    • 2003
  • 최근에 2.5G나 3G 이동 단말 장치를 위한 프로세서로, 다양한 멀티미디어가 가미된 응용구현이 가능하도록 RISC 프로세서와 DSP를 포함하는 단일 칩 프로세서 기술이 등장하고 있다. 이에 따라 듀얼 프로세서 구조에서 비디오 인코딩/디코딩의 처리 속도를 향상시키기 위안 비디오의 인코더/디코더 구조를 제안한다. 기존의 연구에서는 비디오의 인코딩/디코딩의 전 과정을 DSP가 담당하도록 설계하였으나 많은 비트 연산이 필요한 부분에서는 RISC 칩보다 효율성이 낮게 된다. 이러한 문제점을 해결하기 위하여 본 논문에서는 비디오 신호 처리의 인코딩/디코딩을 구성하는 모듈들을 DSP와 RISC의 특성에 맞도록 분리해 수행시킴으로써 효율성을 높이고자 한다.

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An efficient Storage Reclamation Algorithm for RISC Parallel Processing (RISC 병렬 처리를 위한 기억공간의 효율적인 활용 알고리즘)

  • 이철원;임인칠
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.28B no.9
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    • pp.703-711
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    • 1991
  • In this paper, an efficient storage reclamation algorithm for RISC parallel processing in the object orented programming environments is presented. The memory management for the dynamic memory allocation and the frequent memory access in object oriented programming is the main factor that decreases RISC parallel processing performance. The proposed algorithm can be efficiently allocated the memory space of RISCy computer which is required the frequent memory access, so it can be increased RISC parallel processing performance. The proposed algorithm is verified the efficiency by implementing C language on SUN SPARC(4.3 BSD UNIX).

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Cache Architecture Design for the Performance Improvement of OpenRISC Core (OpenRISC 코어의 성능향상을 위한 캐쉬 구조 설계)

  • Jung, Hong-Kyun;Ryoo, Kwang-Ki
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.1
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    • pp.68-75
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    • 2009
  • As the recent performance of microprocessor is improving quickly, the necessity of cache is growing because of the increase of the access time of main memory. Every block of direct-mapped cache maps to one cache line. Although the mapping rule is simple, if different blocks map to one cache line, the miss ratio will be higher than the set-associative cache due to conflicts. In this paper, for the improvement of the direct-mapped cache of OpenRISC, 4-way set-associative cache is proposed. Four blocks of the main memory of the proposed cache map to one cache line so that the miss ratio is less than the direct-mapped cache. Pseudo-LRU Policy, which is one of the Line Replacement Policies, is used for decreasing the number of bits that store LRU value. The OpenRISC core including the 4-way set-associative cache was verified with FPGA emulation. As the result of performance measurement using test program, the performance of the OpenRISC core including the 4-way set-associative cache is higher than the previous one by 50% and the decrease of miss ratio is more than 15%.

Performance and Power Consumption Improvement of Embedded RISC Core (임베디드 RISC 코어의 성능 및 전력 개선)

  • Jung, Hong-Kyun;Ryoo, Kwang-Ki
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.2
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    • pp.453-461
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    • 2010
  • This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of embedded RISC core and a clock-gating algorithm using ODC (Observability Don't Care) operation to improve the power consumption of the core. The branch prediction algorithm has a structure using BTB(Branch Target Buffer) and 4-way set associative cache has lower miss rate than direct-mapped cache. Pseudo-LRU Policy, which is one of the Line Replacement Policies, is used for decreasing the number of bits that store LRU value. The clock gating algorithm reduces dynamic power consumption. As a result of estimation of performance and dynamic power, the performance of the OpenRISC core applied the proposed architecture is improved about 29% and dynamic power of the core using Chartered $0.18{\mu}m$ technology library is reduced by 16%.

제2세대 웍스테이션 "RISC"시스템 6000

  • 김은현
    • Computational Structural Engineering
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    • v.3 no.3
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    • pp.62-65
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    • 1990
  • RISC System/6000은 유닉스 시스템인 AIX를 오퍼레이팅 시스템으로 채택하였고, 기존의 RISC기술에 혁신적인 진보를 이룩하여 가격 대 성능비를 크게 높임과 동시에 시스템의 기능을 극도로 최적화 시킨 새로운 차원의 아이비엠의 고성능 시스템패밀리이다. 이 시스템은 새로운 RISC 시스템 구조인 POWER(Performance Optimization With Enhanced RISC) 개념과 제2세대 수퍼스칼라 기법 및 마이크로 채널 아키텍쳐로 설계되어 있다. 특히 하나의 사이클에서 4개 이상의 명령어를 병렬처리 하도록 설계된 수퍼스칼라 기능을 통하여 복잡한 그래픽 또는 이미지 처리 및 고도의 수치해석 기능이 뛰어나다. RISC시스템/6000은 과학기술계산업무나 멀티사용자의 일반 비즈니스용으로도 모두 뛰어난 범용 컴퓨터로 그래픽 프로세서의 선택과 함께 CAD/CAM이나 그래픽/애니메이션전용 시스템을 구성할 수 있으며, 최고 512 사용자에 이르는 멀티 사용자 시스템을 구성하여 사용할 수 있다. 이전의 유닉스 시스템에 있어서 큰 약점이었던 사용자 인터페이스와 멀티 사용자 및 테스킹이 크게 강화 되었으며, 기존의 IBM 시스템 및 타 기종과도 네트워크 구성이 용이하고 수백여종의 과학기술 적용업무를 이용할 수 있다.

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Virtual Platform based on OpenRISC (OpenRISC 기반의 버츄얼 플랫폼)

  • Jang, HyeongUk;Lee, Jae-Jin;Byun, Kyungjun;Eum, Nakwoong;Jeong, Sangbae
    • Smart Media Journal
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    • v.3 no.4
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    • pp.9-15
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    • 2014
  • A virtual platform models a processor core and the peripheral devices constituting the SoC in software. Major companies utilize a variety of platforms for product development with optimal SW+SoC integrated system architecture design and IP reuse based Top-Down design flow using a virtual platform. In this paper, we propose a virtual platform based on OpenRISC, an open source RISC based core. The proposed virtual platform supports high speed emulation of approximately 20 MIPS using DBT (Dynamic Binary Translation).

Design of RISC-based Transmission Wrapper Processor IP for TCP/IP Protocol Stack (TCP/IP프로토콜 스택을 위한 RISC 기반 송신 래퍼 프로세서 IP 설계)

  • 최병윤;장종욱
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.8 no.6
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    • pp.1166-1174
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    • 2004
  • In this paper, a design of RISC-based transmission wrapper processor for TCP/IP protocol stack is described. The processor consists of input and output buffer memory with dual bank structure, 32-bit RISC microprocessor core, DMA unit with on-the-fly checksum capability, and memory module. To handle the various modes of TCP/IP protocol, hardware-software codesign approach based on RISC processor is used rather than the conventional state machine design. To eliminate large delay time due to sequential executions of data transfer and checksum operation, DMA module which can execute the checksum operation along with data transfer operation is adopted. The designed processor exclusive of variable-size input/output buffer consists of about 23,700 gates and its maximum operating frequency is about 167MHz under 0.35${\mu}m$ CMOS technology.

A design of 32-bit RISC core for PDA (PDA를 위한 32비트 RISC 코어의 설계)

  • 곽승호;최병윤;이문기
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.22 no.10
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    • pp.2136-2149
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    • 1997
  • This paper describes RISC core that has been designed for embedded and protable applications such as PDA or PCS. This RISC processor offers low power consumption and fast context switching. Processor performance is improved by using conditional instruction execution, block data transfer instruction, and multiplication instruction. This architecture is based on RISC principles. The processor adopts 3-stage instruction execution pipeline and has achieved single cycle execution using a 2-phase 40MHz clock. This results in a high instruction throughput and real-time interrupt response. This chip is implemented with $0.6{\mu}m$ triple metal CMOS technology and consists of about 88K transistors. The estimated power dissipation is 179mW.

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Design of Electronic Control Unit for Parking Assist System (주차 보조 시스템을 위한 ECU 설계)

  • Choi, Jin-Hyuk;Lee, Seongsoo
    • Journal of IKEEE
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    • v.24 no.4
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    • pp.1172-1175
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    • 2020
  • Automotive ECU integrates CPU core, IVN controller, memory interface, sensor interface, I/O interface, and so on. Current automotive ECUs are often developed with proprietary processor architectures. However, demends for standard processors such as ARM and RISC-V increase rapidly for saftware compatibility in autonomous vehicles and connected cars. In this paper, an automotive ECU is designed for parking assist system based on RISC-V with open instruction set architecture. It includes 32b RISC-V CPU core, IVN controllers such as CAN and LIN, memory interfaces such as ROM and SRAM, and I/O interfaces such as SPI, UART, and I2C. Fabricated in 65nm CMOS technology, its operating frequency, area, and gate count are 50MHz, 0.37㎟, and 55,310 gates, respectively.

The Design of A Register Allocation Phase for RISC Compilers (RISC 컴파일러 레지스터 할당부 설계)

  • 박종덕;임인칠
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.27 no.8
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    • pp.1211-1220
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    • 1990
  • This paper describes and implements a design method of register allocation as a required module of RISC compiler systems. It compiles a C program to a machine-independent intermediate language, translates each variable into symbolic register. After local allocation process for the symbolic registers, global register allocation is executed by applying the graph coloring algorithm. This register allocation phase is designed for a system with the large register file like RISC machines.

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