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Cache Architecture Design for the Performance Improvement of OpenRISC Core  

Jung, Hong-Kyun (Graduate School of Information and Communication, Hanbat National University)
Ryoo, Kwang-Ki (Graduate School of Information and Communication, Hanbat National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.46, no.1, 2009 , pp. 68-75 More about this Journal
Abstract
As the recent performance of microprocessor is improving quickly, the necessity of cache is growing because of the increase of the access time of main memory. Every block of direct-mapped cache maps to one cache line. Although the mapping rule is simple, if different blocks map to one cache line, the miss ratio will be higher than the set-associative cache due to conflicts. In this paper, for the improvement of the direct-mapped cache of OpenRISC, 4-way set-associative cache is proposed. Four blocks of the main memory of the proposed cache map to one cache line so that the miss ratio is less than the direct-mapped cache. Pseudo-LRU Policy, which is one of the Line Replacement Policies, is used for decreasing the number of bits that store LRU value. The OpenRISC core including the 4-way set-associative cache was verified with FPGA emulation. As the result of performance measurement using test program, the performance of the OpenRISC core including the 4-way set-associative cache is higher than the previous one by 50% and the decrease of miss ratio is more than 15%.
Keywords
Cache; set-associative; OpenRISC;
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