• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.11-15
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• 2002

3 V, 2.46GHz Low Noise Amplifier (LNA) have been designed for standard 0.35$\mu\textrm{m}$ CMOS process with one poly and four metal layers. This design includes on-chip biasing, matching network and multilayer spiral inductors. The single-ended amplifier provides a forward gain of 20.5dB with a noise figure 3.35dB, and an IIP3 of -6dBm while drawing 59mW total Power consumption

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.815-817
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• 2012

본 논문에서는 차량 충돌 예방 레이더 시스템-온-칩용 77GHz 고주파 전단부(RF front-end)를 제안한다. 이러한 고주파 전단부는 77GHz의 동작주파수를 가진 저 잡음 증폭기와 고주파 전력 증폭기로 구성된다. 이러한 회로는 TSMC $0.13{\mu}m$ 혼성신호/고주파 CMOS 공정 ($f_T/f_{MAX}=120/140GHz$)으로 설계되어 있다. 저잡음 증폭기의 경우 전압이득이 36dB로 최근 발표된 연구결과 중 가장 우수한 수치를 보였다. 전력 증폭기는 포화전력과 출력 $P_{1dB}$이 18dBm과 15dBm으로 기존 연구결과 중 가장 우수한 결과를 각각 보였다.

• Information and Communications Magazine
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• v.14 no.3
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• pp.75-86
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• 1997

This manuscript describes the high level system design for the DCP system. The DCP HS and BS transceivers are composed of five systems, including the RF/IF unit, the Analog Front End(AFE), the baseband modem, the voice codec and the micro-controller. In the following, the core transceiver architecture with the primary functions at these subsystem is described.

• ETRI Journal
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• v.41 no.2
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• pp.262-269
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• 2019

This paper introduces a low-cost, high-performance mmWave antenna array module at 77 GHz. Conventional waveguide transitions have been replaced by 3D CPW-microstrip transitions which are much simpler to realize. They are compatible with low-cost substrate fabrication processes, allowing easy integration of ICs in 3D multi-chip modules. An antenna array is designed and implemented using multilayer coupled-fed patch antenna technology. The proposed $16{\times}16$ array antenna has a fractional bandwidth of 8.4% (6.5 GHz) and a 23.6-dBi realized gain at 77 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.4
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• pp.381-391
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• 2010

In this paper, a novel frequency reconfigurable active array antenna(RAA) system, which can be reconfigurable for three reconfigurable frequency bands, is proposed by using commercial RF MEMS switches. The MEMS switch shows excellent insertion loss, linearity, as well as isolation. So, the system performance degradation of the reconfigurable system by using MEMS switches can be minimized. The proposed frequency reconfigurable active antenna system is consisted with the noble frequency reconfigurable front-end amplifiers(RFA) with the simple reconfigurable impedance matching circuits(RMC), reconfigurable antenna elements(RAE), as well as a reconfiguration control board(RCB) for MEMS switch control. The proposed RAA system can be reconfigurable for three frequency bands, 850 MHz, 1.9 GHz, and 3.4 GHz, with $2{\times}2$ array of the RAE having broadband printed dipole antenna topology. The validity of the proposed RFA as well as RAA is also presented with the experimental results of the fabricated systems.

• ETRI Journal
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• v.26 no.3
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• pp.229-240
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• 2004

This paper reports on our development of a dual-mode transceiver for a CMOS high-rate Bluetooth system-onchip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front-end. It is designed for both the normal-rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high-rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual-path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual-mode system. The transceiver requires none of the external image-rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order onchip filters. The chip is fabricated on a $6.5-mm^{2}$ die using a standard $0.25-{\mu}m$ CMOS technology. Experimental results show an in-band image-rejection ratio of 40 dB, an IIP3 of -5 dBm, and a sensitivity of -77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive ${\pi}/4-diffrential$ quadrature phase-shift keying $({\pi}/4-DQPSK)$ mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5-V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low-cost, multi-mode, high-speed wireless personal area network.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1269-1276
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• 2005

In this paper, Mixer using the direct-conversion method intended to use in front-end of a RF receiver is designed. The direct conversion Mixer is an alternative wireless receiver architecture to the well-established superheterodyne, particularly for high integration, low power, and low cost. It operates at 2.4GHz band, and is designed and simulated with a 0.35um CMOS technology and HSPICE simulator. Layout is implemented with a Mentor IC Station. The 2.4GHz CMOS Mixer employs a modified single-balanced Gilbert Cell with additional MOSFET in the output stages to improve IIP2, which is a standard of linearity in direct conversion receiver. Additional coversion-stages's transconductances are controlled by each MOSFET's physical properties. The HSPICE simulation results show that the 2.4GHz CMOS Mixer has voltage gam of 29dB, IIP2 of 63dBm, respectively. The Mixer also draws 3.5mA from a 3.3V supply.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.3
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• pp.674-680
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• 2008

An SDR (Software Defined Radio) system based on general purpose computing platform has benefits of ease of software development process, high degree of software compatibility, and cost-effectiveness of general purpose processors. This paper discusses design and implementation of a dual-mode SDR system that supports both cordless phone and walkie-talky system running on Linux-based general purpose computing platform. For this purpose, we designed modulation and demodulation software on open source-based GNU radio middleware. We also designed a customized RF front-end hardware which performs frequency conversion between RF and IF. The proposed SDR system successfully exhibited its ability to operate both cordless phone and walkie-talky communication on Intel processor-based general purpose computing platform. But experience with the prototype SDR system shows that further research is required for run-time software reconfiguration and efficient integration with conventional TCP/IP protocol stacks.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.9
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• pp.1028-1036
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• 2008

In the OFDM system, IQ imbalance problem happens at the RF front-end of transceiver, which degrades the BER(bit error rate) performance because it affects the constellation in the received signal. Also, phase noise is generated in the local oscillator of transceivers and it destroys the orthogonality between the subcarriers. Conventional PNS algorithm is effective for phase noise suppression, but it is not useful anymore when there are jointly IQ(In-phase and Quadrature) imbalance and phase noise. Therefore, in this paper, we analyze the effect of IQ imbalance and phase noise generated in the down-conversion of the receiver. Then, we estimate and compensate the IQ imbalance and phase noise at the same time. Compared with the conventional method that IQ imbalance after IFFT is estimated and compensated in front of FFT via the feedback, this proposed method extracts and compensates effect of IQ imbalance after FFT stage. In case IQ imbalance and phase noise exist at the same time, we can decrease complexity because it is needless to use elimination of IQ imbalance in time domain and training sequences and preambles. Also, this method shows that it reduces the ICI and CPE component using adaptive forgetting factor of MMSE after FFT.

• Journal of Satellite, Information and Communications
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• v.5 no.1
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• pp.58-62
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• 2010

This paper presents the effects of RF performance parameters on the Galileo receiver design via simulation after reviewing the requirements of the Galileo receiver structure. At first, we considered the general requirements, structure and characteristics of the Galileo system. Then we designed the Galileo receiver focused on performance requirement of 16 dB C/N which is equal to 15 % Error Vector Magnitude(EVM) by using Advanced Design System(ADS) simulation program. In order to verify the function of Automatic Gain Control(AGC)), we measured the IF output power level by changing the input power level at the front - end of the receiver. We analyzed the performance degradation due to phase noise variations of Local Oscillator(LO) in the Galileo receiver through EVM when the minimum sensitivity level of -127 dBm is applied at the receiver. We also analyzed the performance degradation according to variable Analog-to-Digital Converter(ADC) bits within the Dynamic range, -92 ~ -139 dBm, which has been defined by gain range (-2.5 ~ +42.5 dB) in the AGC operation. The results clearly show that the performance of the Galileo receiver can be improved by increasing ADC bits and reducing Phase Noise of LO.