• Title/Summary/Keyword: RF device

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Optical properties of vanadium dioxide thin films on c-Al2O3 (001) substrates by in-situ RF magnetron sputtering

  • Han, Seung Ho;Kang, So Hee;Kim, Hyeongkeun;Yoon, Dae Ho;Yang, Woo Seok
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.23 no.5
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    • pp.224-229
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    • 2013
  • Vanadium oxide thin films were deposited on $c-Al_2O_3$ (001) substrate by in-situ RF magnetron sputtering. Oxygen partial pressure was adjusted to prepare thermochromic $VO_2$ phase. X-ray diffraction patterns and scanning electron microscopy convincingly showed that plate-like $V_2O_5$ grains were changed into round-shape $VO_2$ grains as oxygen partial pressure decreased. After the optimized deposition conditions were fixed, the effect of substrate temperature and orientation on the optical properties of $VO_2$ thin films was analyzed.

Optimization Study on the Epitaxial Structure for 100nm-Gate MHEMTs with InAlAs/InGaAs/GaAs Heterostructure (InAlAs/InGaAs/GaAs 100 nm-게이트 MHEMT 소자의 에피 구조 최적화 설계에 관한 연구)

  • Son, Myung-Sik
    • Journal of the Semiconductor & Display Technology
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    • v.10 no.4
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    • pp.107-112
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    • 2011
  • This paper is for improving the RF frequency performance of a fabricated 100nm ${\Gamma}$-gate MHEMT, scaling down vertically for the epitaxy-structure layers of the device. Hydrodynamic simulation parameters are calibrated for the fabricated MHEMT with the modulation-doped $In_{0.52}Al_{0.48}As/In_{0.53}Ga_{0.47}$As heterostructure grown on the GaAs substrate. With these calibrated parameters, simulations for the vertically-scaled epitaxial layers of the device are performed and analyzed for DC/RF characteristics, including the quantization effect due to the thickness reduction of InGaAs channel layer. A newly designed epitaxy-structure device shows higher extrinsic transconductance, $g_m$ of 1.556 S/mm, and higher frequency performance, $f_T$ of 222.5 GHz and $f_{max}$ of 849.6 GHz.

DC and RF Characteristics of 100-nm mHEMT Devices Fabricated with a Two-Step Gate Recess (2단계 게이트 리세스 방법으로 제작한 100 nm mHEMT 소자의 DC 및 RF 특성)

  • Yoon, Hyung Sup;Min, Byoung-Gue;Chang, Sung-Jae;Jung, Hyun-Wook;Lee, Jong Min;Kim, Seong-Il;Chang, Woo-Jin;Kang, Dong Min;Lim, Jong Won;Kim, Wansik;Jung, Jooyong;Kim, Jongpil;Seo, Mihui;Kim, Sosu
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.30 no.4
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    • pp.282-285
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    • 2019
  • A 100-nm gate-length metamorphic high electron mobility transistor(mHEMT) with a T-shaped gate was fabricated using a two-step gate recess and characterized for DC and microwave performance. The mHEMT device exhibited DC output characteristics having drain current($I_{dss}$), an extrinsic transconductance($g_m$) of 1,090 mS/mm and a threshold voltage($V_{th}$) of -0.65 V. The $f_T$ and $f_{max}$ obtained for the 100-nm mHEMT device were 190 and 260 GHz, respectively. The developed mHEMT will be applied in fabricating W-band monolithic microwave integrated circuits(MMICs).

Impact of Segregation Layer on Scalability and Analog/RF Performance of Nanoscale Schottky Barrier SOI MOSFET

  • Patil, Ganesh C.;Qureshi, S.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.1
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    • pp.66-74
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    • 2012
  • In this paper, the impact of segregation layer density ($N_{DSL}$) and length ($L_{DSL}$) on scalability and analog/RF performance of dopant-segregated Schottky barrier (DSSB) SOI MOSFET has been investigated in sub-30 nm regime. It has been found that, although by increasing the $N_{DSL}$ the increased off-state leakage, short-channel effects and the parasitic capacitances limits the scalability, the reduced Schottky barrier width at source-to-channel interface improves the analog/RF figures of merit of this device. Moreover, although by reducing the $L_{DSL}$ the increased voltage drop across the underlap length reduces the drive current, the increased effective channel length improves the scalability of this device. Further, the gain-bandwidth product in a common-source amplifier based on optimized DSSB SOI MOSFET has improved by ~40% over an amplifier based on raised source/drain ultrathin-body SOI MOSFET. Thus, optimizing $N_{DSL}$ and $L_{DSL}$ of DSSB SOI MOSFET makes it a suitable candidate for future nanoscale analog/RF circuits.

Fabrications and properties of ZnS thin film used as a buffer layer of electroluminescent device (전계발광소자 완충층용 ZnS 박막 제작 및 특성)

  • 김홍룡;조재철;유용택
    • Electrical & Electronic Materials
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    • v.7 no.2
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    • pp.117-122
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    • 1994
  • The role of ZnS buffer layer not only suppresses chemical reactions between emission material and insulating material but also alters the luminescence and the crystallinity of the emission layer, if ZnS buffer layer was sandwiched between emission layer and insulating layer of electroluminescent device. In this research, we fabricated ZnS thin film with rf magnetron sputter system by varying rf power 100, 200W, substrate temperature 100, 150, 200, 250.deg. C and post-annealing temperature 200, 300, 400, 500.deg. C and analysed X-ray diffraction pattern, transmission spectra and cross section by SEM photograph for seeking the optimal crystallization condition of ZnS buffer layer. As a result, increasing the rf power, the crystallinity of ZnS thin film was improved. It was found that the ZnS thin film had better properties than anything else when fabricated with the following conditions ; rf power 200W, substrate temperature 150.deg. C, and post-annealing temperature 400.deg. C. ZnS thin film had the transmittance more than 80% in visible range. So it is suitable to use as a buffer layer of electroluminescent devices.

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Method to specify Subsidiary Device Positioning for Sidelobe Distortion Suppression of Parabolic Antenna (파라볼라 안테나 부엽 왜곡 억제를 위한 부속 장치 위치 지정 방법)

  • Kim, Seungho
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.18 no.4
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    • pp.49-53
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    • 2018
  • Parabolic offset antenna is widely used for wireless communication system. The general structure of parabolic offset antenna system is composed of supporting stand and RF devices under parabolic reflector. However sidelobe distortion in gain pattern is occurred by supporting stand and RF devices. Depending on position of subsidiary devices, angle of sidelobe distortion can be changed. In this paper we describe method for sidelobe distortion suppression using raytracing. We calculate 3D vector for sidelobe distortion suppression zone by raytracing method and compare when subsidiary device is in sidelobe distortion suppression zone or not. By comparison, we show method for parabolic antenna sidelobe distortion suppression.

Integrated Photonic RF Phase Shifter Using an Electrooptic Polymer Modulator (전기광학폴리머 변조기틀 이용한 집적광학적 RF 위상변환기)

  • 이상신
    • Korean Journal of Optics and Photonics
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    • v.15 no.3
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    • pp.274-277
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    • 2004
  • An integrated photonic radio frequency (RF) phase shifter has been proposed and fabricated using a nested dual Mach-Zehnder modulator configuration in a new electro-optic polymer. The fabricated device shows a continuous voltage control of the RF signal phase. A near-linear phase shift exceeding 108$^{\circ}$was obtained for a 16-GHz microwave signal by tuning the do control voltage over a 7.8- $V_{pp}$ range.e.

Novel Defect Testing of RF Front End Using Input Matching Measurement (입력 매칭 측정을 이용한 RF Front End의 새로운 결함 검사 방법)

  • 류지열;노석호
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2003.10a
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    • pp.818-823
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    • 2003
  • 본 논문에서는 입력 매칭(input matching) BIST(Built-In Self-Test) 회로를 이용한 RF font end의 새로운 결함 검사방법을 제안한다. BIST 회로를 가진 RF front end는 1.8GHz LNA(Low Noise Amplifier: 저 잡음 증폭기)와 이중 대칭 구조의 Gilbert 셀 믹서로 구성되어 있으며, TSMC 0.25$\mu\textrm{m}$ CMOS 기술을 이용하여 설계되었다. catastrophic 결함 및 parametric 변동을 가진 RF front end와 결함을 갖지 않은 RF front end를 판별하기 위해 RF front end의 입력 전압 특성을 조사하였다. 본 방법에서는 DUT(Device Under Test: 검사대상이 되는 소자)와 BIST 회로가 동일한 칩 상에 설계되어 있기 때문에 측정할 때 단지 디지털 전자계와 고주파 전압 발생기만이 필요하며, 측정이 간단하고 비용이 저렴하다는 장점이 있다. BIST 회로가 차지하는 면적은 RF front end가 차지하는 전체면적의 약 10%에 불과하다. 본 논문에서 제안하는 검사기술을 이용하여 시뮬레이션해 본 결과 catastrophic 결함에 대해서는 100%, parametric 변동에 대해서는 약 79%의 결함을 검출할 수 있었다.

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A Wireless Glove-Based Input Device for Wearable Computers

  • An, Sang-Sup;Park, Kwang-Hyun;Kim, Tae-Hee;Jeon, Jae-Wook;Lee, Sung-Il;Choi, Hyuck-Yeol;Choi, Hoo-Gon
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.1633-1637
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    • 2003
  • Existing input devices for desktop computers are not suitable for wearable computers because they are neither easy to carry nor convenient to use in a mobile working environment. Different input devices for wearable computers must be developed. In this paper, a wireless glove-based input device for wearable computers is proposed. The proposed input device consists of a pair of chording gloves. Its keys are mounted on the fingers and their chording methods are similar to those of a Braille keyboard. RF (Radio Frequency) and IrDA (Infrared Data Association) modules are used to make the proposed input device wireless. Since the Braille representation for numbers and characters is efficient and has been well established for many languages in the world, the proposed input device may be one of good input devices to computers. Furthermore, since the Braille has been used for visually impaired people, the proposed one can be easily used as an input device to computers for them.

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A Study on AC Modeling of the ESD Protection Devices (정전기 보호용 소자의 AC 모델링에 관한 연구)

  • Choi, Jin-Young
    • Journal of IKEEE
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    • v.8 no.1 s.14
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    • pp.136-144
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    • 2004
  • From the AC analysis results utilizing a two dimensional device simulator, the ac equivalent-circuit modeling of the ESD protection devices is executed. It is explained that the ac equivalent circuit of the NMOS protection transistor is modeled by a rather complicated form and that, depending on the frequency range, the error can be large if it is modeled by a simple RC serial circuit. It is also shown that the ac equivalent circuit of the thyristor-type pnpn protection device can be modeled by a simple RC serial circuit. Based on the circuit simulations utilizing the extracted equivalent circuits, the effects of the parasitics in the protection device on the characteristics of LNA are examined when the LNA, which is one of the important RF circuits, is equipped with the protection device. It is explained that a large error can result in estimating the circuit characteristics if the NMOS protection transistor is modeled by a simple capacitor. It is also confirmed that the degradation of the LNA characteristics by incorporating the ESD protection device can be reduced a lot by adopting the suggested pnpn device.

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