• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.15 no.7
• /
• pp.730-735
• /
• 2004

This paper describes what brings about DC offset and the impact or the DC offset on the performance or direct-conversion mobile receiver in WCDMA system. The performance degradation of $E_{b}/N_{o}$ due to the DC offset is presented through simulation result. Direct-conversion RF Transceiver which has the function of DC offset control is implemented and then applied to the WCDMA test-bed for the performance evaluation. The receiver performance degradation of $E_{c}/I_{o}$ is evaluated and analyzed by varying DC offset value. The practical test showed the minimum requirement of DC offset value to meet system performance.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.5
• /
• pp.595-604
• /
• 2016

Utilizing a standard 130-nm CMOS process, a RF frontend is designed at 24 GHz for automotive collision avoidance radar application. Single IF direct conversion receiver (DCR) architecture is adopted to achieve high integration level and to alleviate the DCR problem. The proposed frontend is composed of a two-stage LNA and downconversion mixers. To save power consumption, and to enhance gain and linearity, stacked NMOS-PMOS $g_m$-boosting technique is employed in the design of LNA as the first stage. The switch transistors in the mixing stage are biased in subthreshold region to achieve low power consumption. The single balanced mixer is designed in PMOS transistors and is also realized based on the well-known folded architecture to increase voltage headroom. This frontend circuit features enhancement in gain, linearity, and power dissipation. The proposed circuit showed a maximum conversion gain of 19.6 dB and noise figure of 3 dB at the operation frequency. It also showed input and output return losses of less than -10 dB within bandwidth. Furthermore, the port-to-port isolation illustrated excellent characteristic between two ports. This frontend showed the third-order input intercept point (IIP3) of 3 dBm for the whole circuit with power dissipation of 6.5 mW from a 1.5 V supply.

• The Bulletin of The Korean Astronomical Society
• /
• v.37 no.1
• /
• pp.66.1-66.1
• /
• 2012

We have developed superconducting mixer receivers for 129 GHz VLBI observation in Korean VLBI Network(KVN). The developed mixer has a radial waveguide probe with simple transmission line LC transformer as a tuning circuit to its 5 series-connected junctions, which can have 125-165 GHz as operation RF frequency. For IF signal path a high impedance quarter-wavelength line connects the probe to one end of symmetric RF chokes. DSB receiver noise of the mixer was about 40 K over 4-6 GHz IF band whereas we achieved about uncorrected SSB noise temperature of 70 K and better than 10 dB IRR in 2SB configuration with 8-10 GHz IF band. Insert-type receiver cartridges using the mixers have been assembled for all three KVN stations. On-site performance summary in commissioning phase is presented.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.22 no.7
• /
• pp.729-736
• /
• 2011

In this paper, we propose a varactor-diodeless voltage-controlled oscillator operating at X-band, and verify the possibility of applying to a receiver for microwave radar signal detection applications. The proposed VCO is realized by only single RF BJT device as a varactor diode is substitued by a intrinsic collector-base PN-junction of the active device which is used to generate negative resistance. The fabricated VCO meets the specification of the receiver, which has a 11.20~11.75 GHz tuning bandwidth with respect to the tuning voltage, 1.0~7.0 V, output power of 9.0~12.0 dBm and linear frequency tuning performance.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.615-616
• /
• 2006

Nowadays, the need of multi-mode/multi-band transceiver is rapidly increasing, so we design a direct conversion RF front-end for multi-mode/multi-band receiver that support WCDMA/CDMA2000/WIBRO standard. It consists of variable gain reconfigurable LNA and single input double balanced Mixer and complementary differential LC Oscillator. The circuit is implemented in 0.18 um RF CMOS technology and is suitable for low-cost mode/multi-band.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.11 no.1
• /
• pp.110-115
• /
• 2000

A K-band GaAs MMIC receiver module has been developed using 0.15 ${\mu}{\textrm}{m}$ HEMT technology process. It incorporates two front end low noise amplifiers, a double balanced diode mixer, and filters. The RF input frequency ranges 20.1 to 21 GHz and the IF output 1.1 to 2 GHz. Test results show an overall conversion gain of more than 27 dB, and less than a 2.2 dB noise figure. The image-rejection ratio greater than 21 dB has been obtained. The isolation between RF and IF ports is better than 27 dB, and between LO and IF is more than 50 dB.

• International journal of advanced smart convergence
• /
• v.11 no.4
• /
• pp.41-46
• /
• 2022

This study is a Ku-band array antenna for the manufacture of low-orbit satellite communication terminals, designed to have miniaturization, high gain, and wide beam width. The transmission of low-orbit satellite communication has a right-rotating circularly polarized wave, and the reception has a left-rotating circularly polarized wave. The 4×8 array antenna was separated for transmission and reception, and it was combined with the RF circuit part of the transmitter and receiver, and was terminated in the form of a waveguide for RF signal impedance matching in the form of a transition from the microstrip line to the waveguide. The 30° beam width of the receiver maximum gain of 19 dBi and the 29° beam width of the transmitter maximum gain of 18 dBi are shown. Through this antenna configuration, the system was configured to suit the low-orbit satellite transmission/reception characteristics.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.2
• /
• pp.111-116
• /
• 2003

In this paper, a CMOS baseband analog receiver for wireless home network is discussed. It is composed of a Gilbert type mixer, an Elliptic 6th order 1ow pass filter, and a 6-bit A/D converter. The main role of the mixer is generating a mixed analog signal between the 200MHz output signal of CMOS RF stage and the 199MHz local oscillator. After the undesired high frequency component of the mixed signal comes out. Finally, the analog signal is converted into digital code at the 6-bit A/D converter, The proposed receiver is fabricated with 0.25${\mu}{\textrm}{m}$ 1-poly 5-metal CMOS technology, and the chip area is 200${\mu}{\textrm}{m}$ X1400${\mu}{\textrm}{m}$. the receiver consumes 130㎽ at 2.5V power supply.

• Journal of Satellite, Information and Communications
• /
• v.4 no.1
• /
• pp.36-44
• /
• 2009

The key technologies of GNSS receiver for GNSS sensor station are under development as a part of a GNSS ground station in ETRI. This paper presents the GNSS receiver implementation and signal processing result which is implemented based on FPGA to process the Galileo E1 and E5 signal. To verify the working and performance for GNSS receiver which is implemented based on FPGA, live signal received from GIOVE-B which is second test satellite is used. We gather GIOVE-B signal by using prototyping antenna and RF/IF units including IF-component. To verify Galileo E1 and E5 signal processing function from GIOVE-B, FPGA based signal processing module is implemented as a prototyping hardware board.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.2
• /
• pp.100-105
• /
• 2010

In this paper, a FM radio receiver integrated circuit has been developed based on $0.5{\mu}m$ CMOS process for Zero-Crossing FM demodulator over the 88MHz to 108MHz band. The receiver is designed with the low-IF architecture, and includes Low Noise Amplifier(LNA), Down-Conversion Mixer, Phase Locked Loop(PLL), IF LPF, and a comparator. The measured results of the LNA and Mixer show that the conversion gain of 23.2 dB, the input PldB of -14 dBm, and the noise figure of 15 dB. The measured analog block of the LPF and comparator show the voltage gain of over 89 dB, and the IF LPF can configure the passband from 600KHz to 1.3MHz with 100KHz step through the internal control register banks. The designed FM radio receiver operates at 4.5V with the total current consumption of 15.3mA, so the total power consumption is about 68.85mW. The commercial FM radio has been successfully received.