• Journal of the Microelectronics and Packaging Society
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• v.7 no.3
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• pp.19-25
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• 2000

In this paper, we describe RF receiver module for IMT-2000 handset with 5 MHz channel bandwidth. The fabricated RF receiver module consists of Low Noise Amplifier, RF SAW filter, Down-converter, If SAW filter, AGC and PLL Synthesizer. The NF and IIP3 of LNA is 0.8 dB, 3 dBm at 2.14 GHz, conversion gain of down-converter is 10 dB, dynamic range of AGC is 80 dB, and phase noise of PLL is -100 dBc at 100 kHz. The receiver sensitivity is -110 dBm, adjacent channel selectivity is 48 dBm.

• Progress in Superconductivity and Cryogenics
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• v.14 no.1
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• pp.44-47
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• 2012

The substantial improvement of the signal-to-noise ratio (SNR) can be achieved with small-size samples or low-field MRI system by high-temperature superconducting(HTS) RF coil. The typical HTS RF coil made of HTS thin film is expensive and is limited the coil geometry to planar surface coil. In this study, commercial Bi-2223 HTS tapes was used as RF coil for a 0.35T permanent MRI system. It has advantages of both much lower cost and easier fabrication over HTS thin film coil. SNR gain of the image obtained from the HTS RF coil over a conventional Cu RF coil at room temperature was about 2.4-fold and 1.9-fold using the spin echo pulse sequence and gradient echo pulse sequence respectively.

• Journal of the Korea Society of Computer and Information
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• v.24 no.7
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• pp.71-78
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• 2019

This paper describes a design for a RF receiver to receive satellite digital audio service. The RF receiver designed in this study is a planar structure that is easy to install on the rooftop of a car and is compact in size. In addition, it can be applied to certain commercial models because it has low noise and high gain characteristics. The impedance bandwidth of antenna is 17.8%(415MHz), and the axial ratio is below 3dB as good properties for the bandwidth of 40MHz which is a satellite digital audio service band. Also, it had a broad radiation beamwidth of $95.41^{\circ}$ in H-plane and $117.45^{\circ}$ in E-plane. From the results of the field test of satellite digital audio service reception for the RF receiver, it demonstrated good C/N rate(10.2dB).

• ETRI Journal
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• v.28 no.3
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• pp.355-363
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• 2006

This paper presents a low-cost RF parameter estimation technique using a new RF built-in self-test (BIST) circuit and efficient DC measurement for 4.5 to 5.5 GHz low noise amplifiers (LNAs). The BIST circuit measures gain, noise figure, input impedance, and input return loss for an LNA. The BIST circuit is designed using $0.18\;{\mu}m$ SiGe technology. The test technique utilizes input impedance matching and output DC voltage measurements. The technique is simple and inexpensive.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.3
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• pp.632-638
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• 2011

This paper presents on-chip Design-for-Testability (DFT) circuit for radio frequency System-on-Chip (SoC) applications. The proposed circuit measures functional specifications of RF integrated circuits such as input impedance, gain, noise figure, input voltage standing wave ratio (VSWRin) and output signal-to-noise ratio (SNRout) without any expensive external equipment. The RF DFT scheme is based on developed theoretical expressions that produce the actual RF device specifications by output DC voltages from the DFT chip. The proposed DFT showed deviation of less than 2% as compared to expensive external equipment measurement. It is expected that this circuit can save marginally failing chips in the production testing as well as in the RF system; hence, saving tremendous amount of revenue for unnecessary device replacements.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.10
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• pp.966-982
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• 2014

This paper presents recent trends in system-level EMC investigation and countermeasure technology for radio frequency interference (RFI) influenced by noise generated in high-speed digital system. Recently, as the only digital device can perform various roles, there are a variety of EMI/EMC problems between systems. Especially, RFI is now recognized as a major problem, which occurs by EMI caused by the digital system. Therefore, in this paper, recent trends of RFI investigation from component-level to system-level are introduced and analyzed. Furthermore, in order to solve the RFI problem, recent researches are presented and investigated for the occurrences and suppression methods of common-mode noise which is one of the major noise sources in high-speed digital system. Lastly, this paper suggested future research of system-level EMC analysis and countermeasure technology for RFI problems.

• Journal of Advanced Navigation Technology
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• v.12 no.6
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• pp.604-610
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• 2008

A 2.4 GHz CMOS RF front-end using for ZigBee application is described The front-end consists of a low noise amplifier and a down-mixer and uses a 2 MHz IF frequency. A common source with resistive feedback and an inductive degeneration are adopted for a low noise amplifier, and a 20 dB gain control step is digitally controlled. A passive mixer for low current consumption is employed. The RF front-end is implemented in 0.18 ${\mu}m$IP6M CMOS process. The measured performance is 4.44 dB NF and -6.5 dBm IIP3 while consuming 3.28 mA current from a 1.8 V supply.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.423-424
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• 2011

This paper has proposed a 920 MHz RF front-end for IEEE 802.15.4g SUN (Smart Utility Network) systems. The proposed 920 MHz RF front-end consists of a driver amplifier, a low noise amplifier, and a RF switch. In the TX mode, the driver amplifier has been designed as a single-ended topology to remove a transformer which causes a loss of the output power from the driver amplifier. In addition, a RF switch is located in the RX path not the TX path. In the RX mode, the proposed low noise amplifier can provide a differential output signal when a single-ended input signal has been applied to. A LC resonant circuit is used as both a load of the drive amplifier and a input matching circuit of the low noise amplifier, reducing the chip area. The proposed 920 MHz RF Front-end has been implemented in a 0.18-um CMOS technology. It consumes 3.6 mA in driver amplifier and 3.1 mA in low noise amplifier from a 1.8 V supply voltage.

• Journal of IKEEE
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• v.19 no.3
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• pp.371-377
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• 2015

This paper is about the RF transceiver designed and implementation for common data link. The trasmitter is configured as a frequency up-converter, a power amplifier and a duplexer. The receiver is configured as a duplxer, a frequency down-converter and a low noise amplifier. The maximum transmission distance, the reception sensitivity is designed to meet the electrical and temperature characteristics and the like. Using a modeling and simulation in order to meet the requirements of the RF transceiver has been designed and implemented. Transmitting output power and Noise Figure has been measured with 38.58dBm and 5.5dB, respectively. All of the electrical and temperature specifications was meet. Was confirmed all of the requirement specification by electrical characteristics test and temperature characteristics test.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.2
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• pp.83-87
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• 2004

Phase noise performance and current consumption of Radio Frequency (RF) Voltage-Controlled Oscillator (VCO) are largely dependent on the Quality (Q) factor of inductor-capacitor (LC) tank. Because the Q-factor of LC tank is determined by on-chip spiral inductor, we designed, analyzed, and modeled on-chip differential inductor to enhance differential Q-factor, reduce current consumption and save silicon area. The simulated inductance is 3.3 nH and Q-factor is 15 at 2 GHz. Self-resonance frequency is as high as 13 GHz. To verify its use to RF applications, we designed 2 GHz differential LC VCO. The measurement result of phase noise is -112 dBc/Hz at an offset frequency of 100 kHz from a 2GHz carrier frequency. Tuning range is about 500 MHz (25%), and current consumption varies from 5mA to 8.4 mA using bias control technique. Implemented in $0.35-{\mu}m$ SiGe BiCMOS technology, the VCO occupies $400\;um{\times}800\;um$ of silicon area.