• Title/Summary/Keyword: RF Noise

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$0.18{\mu}m$ CMOS Quadrature VCO for IEEE 802.11a WLAN Application

  • Son, Chul-Ho;Kim, Bok-Ki
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.529-530
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    • 2008
  • The proposed CMOS Quadrature VCO for WLAN application was designed in TSMC $0.18\;{\mu}m$ RF CMOS technology. The QVCO based on NMOS back-gate as a coupling transistor and switched capacitors array without tail transistors is designed to generate quadrature output signals. The simulated results show that the QVCO core consumed 3.67 mA and 6.6 mW from a 1.8 V supply. The QVCO is tunable between $4.76\;GHz\;{\sim}\;6.35\;GHz$ and has a phase noise lower than -116.8 ㏈c/Hz at 1 MHz offset over the entire tuning range

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Analysis of a Distributed Mixer Using Dual-gate MESFETSs (Dual-gate MESFET를 사용한 분포형 혼합기 해석에 관한 연구)

  • 김갑기;오양현;정성일;이종익
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.7 no.2
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    • pp.178-185
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    • 1996
  • In this paper, a theoretical analysis of a wide band distributed mixer using a dual-gate GaAs MESFET's(DGFET) is introduced. Based on low noise mixer mode(LNM) region modeling of DGFET, variation of g/sub m/ and conversion gain are presented versus bias. The distributed mixer is composed of drain and gate transmission line, m-derived image impedance matching circuits at each input and output port, and DGFET's. Through computer simulation, wide-band characteristics of designed distributed mixer are confirmed. And, it is certificated that LO/RF isolation between gate 1 and gate 2 is obtained more than 15dB.

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High-Frequency Modeling and the Influence of Decoupling Capacitors in High-Speed Digital Circuits (고속 고밀도 디지털 회로에서 사용되는 디커플링 캐패시터의 고주파 모델링과 영향)

  • 손경주;김진양;이해영;최철승;변정건
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2000.11a
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    • pp.23-27
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    • 2000
  • Simultaneous Switching Noise (SSN) propagated through parallel power and ground planes in high-speed multilayer printed circuit boards (PCBs) causes malfunction of both digital and analog circuits. To reduce SSN, decoupling capacitors are generally used in the PCBs. In this paper, we improve the equivalent circuit model of decoupling capacitor in high-frequency range to analyze the effect of SSN reduction accurately. The analysis is performed by the microwave and RF design system (MDS) method and the finite difference time domain (FDTD) method. We compared the results by the ideal capacitor model with those by the proposed model.

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An Ultra Low Cost, Dual-band VCO Design at GSM/DCN (저 비용 듀얼 대역 전압 제어 발진기 설계)

  • 오태성;이영훈
    • Proceedings of the Korea Electromagnetic Engineering Society Conference
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    • 2001.11a
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    • pp.235-238
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    • 2001
  • 단일 단말기로부터 멀티 통신이 가능하게 됨에 따라 광대역 또는 듀얼대역에서 사용되는 RF 소자 개발이 중요시되고 있다. 그러므로 소형, 저 비용의 멀티대역 VCO(Voltage Controlled Oscillator)개발이 요구된다. 본 논문에서 GSM/DCN 대역에서 사용 가능한 듀얼밴드 VCO을 설계하였다. 하나의 발진부, 듀얼 공진부, 완충증폭기, 스위치회로로 구성되었으며, 위상 보정 기법을 이용하여 각 밴드에 대한 발진 조건을 만족시키므로 사용 부품의 수를 줄일 수 있어 저 비용, 소형화, 낮은 위상잡음(phase noise)을 얻을 수 있다. 설계된 듀얼 VCO는 GSM 대역에서 -110dBc/Hz(100kHz offset) 이하의 위상 잡음과 DCN 대역에서 -108dBc/Hz(100kHz offset)의 위상 특성을 보인다. 출력전력은 0$\pm$3dBm이며 소비전력 7mA로 만족할만한 성능을 보인다.

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Design of a Frequency Synthesizer for UHF RFID Reader Application (UHF 대역 RFID 리더 응용을 위한 주파수합성기 설계)

  • Kim, Kyung-Hwan;Oh, Kun-Chang;Park, Jong-Tae;Yu, Chong-Gun
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.57 no.5
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    • pp.889-895
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    • 2008
  • In this paper a Fractional-N frequency synthesizer is designed for UHF RFID readers. It satisfies the ISO/IEC frequency band($860{\sim}960MHz$) and is also applicable to mobile RFID readers. A VCO is designed to operate at 1.8GHz band such that the LO pulling effect is minimized. The 900MHz differential I/Q LO signals are obtained by dividing the differential signal from an integrated 1.8GHz VCO. It is designed using a $0.18{\mu}m$ RF CMOS process. The measured results show that the designed circuit has a phase noise of -103dBc/Hz at 100KHz offset and consumes 9mA from a 1.8V supply. The channel switching time of $10{\mu}s$ over 5MHz transition have been achieved, and the chip size including PADs is $1.8{\times}0.99mm^2$.

Design of 24GHz Low Noise Amplifier for Automotive Collision Avoidance Radar (차량 충돌 예방 레이더 시스템-온-칩용 77GHz 고주파 전단부 설계)

  • Kim, Shin-Gon;Lee, Jung-Hoon;Ryu, Jee-Youl;Noh, Seok-Ho
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.10a
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    • pp.815-817
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    • 2012
  • 본 논문에서는 차량 충돌 예방 레이더 시스템-온-칩용 77GHz 고주파 전단부(RF front-end)를 제안한다. 이러한 고주파 전단부는 77GHz의 동작주파수를 가진 저 잡음 증폭기와 고주파 전력 증폭기로 구성된다. 이러한 회로는 TSMC $0.13{\mu}m$ 혼성신호/고주파 CMOS 공정 ($f_T/f_{MAX}=120/140GHz$)으로 설계되어 있다. 저잡음 증폭기의 경우 전압이득이 36dB로 최근 발표된 연구결과 중 가장 우수한 수치를 보였다. 전력 증폭기는 포화전력과 출력 $P_{1dB}$이 18dBm과 15dBm으로 기존 연구결과 중 가장 우수한 결과를 각각 보였다.

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The Design of Low Noise Downconverter for K-band Satellite Multipoint Distribution Service (K-band SMDS용 저잡음 하향변환기의 설계)

  • 정인기;이강훈;이대원;이영철
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2001.05a
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    • pp.228-231
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    • 2001
  • 본 논문에서는 K-band SMDS용 하향변환기를 설계 및 제작하였다. SMDS용 하향변환기는 입력신호 주파수 19.2㎓~20.2㎓에 대한 3단 저잡음 증폭기, 대역통과필터, 18.25㎓의 국부발진기, 및 IF단으로 구성하였고 3단 저잡음 증폭기의 이득은 28dB를 나타내었다. 국부 발진기는 고안정 특성을 위하여 유전체 공진 발진기로 구성하여 주파수 18.25㎓에서 0.5dBm의 출력전력을 나타냈으며, 19.2㎓~20.2㎓의 RF신호를 드레인형 FET믹서에 인가하였을 때 950MHz ~1950MHz 범위에서 변환이득은 5dB를 나타내었다. 본 논문에서 국내 K-band 위성인터넷을 위한 하향변환기의 규격을 만족시킬 수 있었다.

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A Study on the Design and Implementation of SDLA for C-Band Application (C-Band용 SDLA의 설계 및 구현에 관한 연구)

  • 임경택;윤기방;조홍구
    • Proceedings of the Korea Society for Industrial Systems Conference
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    • 2000.11a
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    • pp.711-727
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    • 2000
  • In this paper, the design of the successive detection logarithmic amplifier(SDLA) is reviewed for radar and EW system, and implemented in hybrid MIC. The SDLA operates over the 5 to 7㎓ frequency range. the unit has a dynamic range of -80㏈m to 0㏈m, a logging accuracy of ±1.4㏈, a legging slope 19.2㎷/㏈, and a gain flatness of ± 1.2㏈. Input VSWR of less than 2, noise figure of 2㏈, video impedance of 900Ω and output voltage range of 0 to 1.53V DC have been obtained over 80㏈ of dynamic range.

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High Performance On-Chip Integrable Inductor for RF Applications

  • Lee, J.Y.;Kim, J.H.;Kim, M.J.;Moon, S.S.;Kim, I.H.;Lee, Y.H.;Yook, Jong-Gwan;Kukjin Chun
    • Journal of the Semiconductor & Display Technology
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    • v.2 no.1
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    • pp.11-14
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    • 2003
  • The high Q(quality factor) suspended spiral inductors were fabricated on the silicon substrate by 3D surface micromachined process. The integration of 2.4GHz VCO has been performed by fabricating suspended spiral inductor of the top of CMOS VCO circuit. The phase noise of VCO integrated MEMS inductor is 93.5 dBc/Hz at 100kHz of offset frequency.

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A Study on the Development of Dual-band PLL Frequency Synthesizer for miniature Repeater (초소형 중계기용 듀얼 밴드 주파수합성기 개발에 관한 연구)

  • 나영수;김진섭;강용철;변상기;나극환
    • Proceedings of the IEEK Conference
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    • 2003.11c
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    • pp.37-40
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    • 2003
  • The 1.63㎓, 2.33㎓ dual-band PLL frequency synthesizer has been developed for applications to the miniature repeater. The miniature dual-band repeater will be used at shopping mall, basements and underground parking lots. The in-loop 1.63㎓, 2.33㎓ dual-band PLL frequency synthesizer has been developed by designing Si BJT VCO and PLL loop circuits with Colpitts. The prototype of 1.63㎓, 2.33㎓ dual-band PLL frequency synthesizer of size 19${\times}$19${\times}$8(mm) has shown operating frequencies of 1.63㎓, 2.33㎓ ranges, RF output of 1dBm(PCS), 1dBm(IMT-2000), phase noise of -100 dBc/Hz(PCS), -95dBc/Hz(IMT-2000) at 10KHz offset, harmonics suppression of -24dB c(PCS), -15dBc(IMT-2000).

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