• Journal of the Microelectronics and Packaging Society
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• v.8 no.4
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• pp.11-15
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• 2001

In this paper, hermetic sealing technology was studied for wafer level packaging of the RF-MEMS devices. With the flip-chip bonding method. this non-conductive B-stage epoxy sealing will be profit to the MEMS device sealing. It will be particularly profit to the RF-MEMS device sealing. B-stage epoxy can be cured by 2-step and hermetic sealing can be obtained. After defining 500 $\mu\textrm{m}$-width seal-lines on the glass cap substrate by screen printing, it was pre-baked at $90^{\circ}C$ for about 30 minutes. It was, then, aligned and bonded with device substrate followed by post-baked at $175^{\circ}C$ for about 30 minutes. By using this 2-step baking characteristic, the width and the height of the seal-line could be maintained during the sealing process. The height of the seal-line was controlled within $\pm$0.6 $\mu\textrm{m}$ in the 4 inches wafer and the bonding strength was measured to about 20MPa by pull test. The leak rate, that is sealing characteristic of the B-stage epoxy, was about $10^{-7}$ cc/sec from the leak test.

• Ceramist
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• v.8 no.3
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• pp.25-30
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• 2005

최근 SOP에 대한 관심이 늘어나고 있으며 그에 따라 새로운 재료에 대한 관심도 증폭되고 있다. 예전의 단순한 신호 전달의 매개체 역할에서 벗어나 많은 수동 소자나 RF소자들을 내장하고 궁극적으로는 능동 소자까지 단일 기판위에 탑재하기 위해서는 기존의 RF 적인 전기적인 요구 특성 위에 많은 부가 특성들이 요구된다. 특히 SI이나 GaAs같은 능동 소자들과의 Assembly과정에서의 신뢰성을 확보하기 위해 낮은 선팽창 계수나 높은 탄성 계수 등의 기계적인 특성들이 요구되고 있으며 또한 점차 복잡한 회로 구조 등을 구현하기 위해 무수축이라는 새로운 공법 또한 요구되어 지고 있다. 그리고 사용주파수가 점차 높아짐에 따라 한편으로는 저유전율과 저손실의 재료가 요구되고 있으며 다른 한편으로는 embedded Capacitance의 요구에 맞춰 고유전율의 기판재료 또한 요구되어 지고 있다. 따라서 궁극적으로는 회로 구현의 목적에 따라 저유전율과 고유전율의 이종 재료의 접합이라는 문제 또한 자연스럽게 대두되고 있다. 이처럼 SoP에 대한 시장의 요구가 증가함에 따라 새로운 재료개발의 요구 또한 늘어나게 될 것으로 예상된다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2002.05a
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• pp.133-133
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• 2002

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.75-87
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• 2010

For two input-protection schemes suitable for RF ICs utilizing the thyristor and diode protection devices, which can be fabricated in standard CMOS processes, we attempt an in-depth comparison on HBM ESD robustness in terms of lattice heating inside protection devices and peak voltages developed across gate oxides in input buffers, based on DC, mixed-mode transient, and AC analyses utilizing a 2-dimensional device simulator. For this purpose, we construct an equivalent circuit for an input HBM test environment of a CMOS chip equipped with the input ESD protection circuits, which allows mixed-mode transient simulations for various HBM test modes. By executing mixed-mode simulations including up to six active protection devices in a circuit, we attempt a detailed analysis on the problems, which can occur in real tests. In the procedure, we suggest to a recipe to ease the bipolar trigger in the protection devices and figure out that oxide failure in internal circuits is determined by the junction breakdown voltage of the NMOS structure residing in the protection devices. We explain the characteristic differences of two protection schemes as an input ESD protection circuit for RF ICs, and suggest valuable guidelines relating design of the protection devices and circuits.

• 전기의세계
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• v.43 no.1
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• pp.20-22
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• 1994

이동통신은 그 방식이 아날로그든 디지틀이든 같은 기능의 음성신호를 송신하고 수신하는 것이다. 아나로그형은 크게 RF 수신부, RF 송신부, 신호처리부 제어부 그리고 전원부로 나누어 진다. 통화시 송,수신이 동시에 이루어지므로 송신신호와 수신신호가 서로 간섭하지 않도록 정교환 신호 여과기가 필요하다. Philips사의 경우 몇개의 칩으로 RF/IF 변환, 아나로그 신호처리 그리고 신호제어를 할 수 있도록 설계하였고 몇몇 선두회사들은 하나의 아나로그 처리기로 baseband 아나로그 신호를 처리 할 수 있도록 설계하였다. RF 부분은 아직 별도의 PCB에 제작되는데 이유는 IF 부분의 송.수신부가 공간을 많이 차지하며, RF 부분에는 가격을 내리기 위해 개별 소자들이 많이 쓰이기 때문이다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.13-18
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• 2007

This paper presents the experimental findings on the different degradation mechanism which depends on the gate oxide thickness in lateral DMOS transistors. For thin oxide devices, the generation of interface states in the channel region and the trapped holes in the drift region is found to be the causes of the device degradation. For thick devices, the generation of interface states in the channel region is found to be the causes of the device degradation. We confirmed the different degradation mechanism using device simulation. From the comparison of device degradation under DC and AC stress, it is found that the device degradation is more significant under DC stress than one under AC stress. The device degradation under AC stress is more significant in high frequency. Therefore the hot carrier induced degradation should be more carefully considered in the design of RF LDMOS transistors and circuit design.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.1 s.92
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• pp.102-112
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• 2005

In this work, we developed fully integrated broadband MMIC chip set employing CSP(Chip Size Package) for K/Ka band applications. By utilizing an ACF for the RF-CSP, the fabrication process for the packaged amplifier MMIC could be simplified and made cost effective. $STO(SrTi_{3})$ capacitors were employed to integrate the DC biasing components on the MMIC, and LC parallel circuits were employed for DC feed and ESD protection. A pre-matching technique and RC parallel circuit were used to achieve a broadband matching and good stability fer the amplifier MMIC in K/Ka band. The amplifier CSP MMIC exhibited good RF performance over a wide frequency range in K/Ka band. This work is the first report of a fully integrated CSP amplifier MMIC successfully operating in the K/Ka band.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.105-105
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• 2012

본 논문에서는 전세계적으로 차세대 에너지절감 반도체로 각광을 받고 있는 GaN 소자의 연구개발 동향에 관하여 발표하고자 한다. GaN 반도체는 와이드 밴드갭(Eg=3.4eV)과 고온 안정성($700^{\circ}C$)등 재료적인 특징으로 인하여 고출력 RF 전력증폭기와 고전력용 전력반도체 응용에 큰 장점을 가진다. 고출력용 GaN RF 전력증폭 소자의 전력밀도는 기존 Si-기반 LDMOS 트랜지스터보다 10배 이상 높아 제품의 소형화와 경량화를 통하여 30% 이상의 전력절감이 가능하며, 레이더, 위성등 송수신 트랜시버 모듈에 GaN 전력증폭기를 이용할 경우 기존 GaAs-기반 전력증폭기에 비하여 높은 전력밀도(>x8)와 높은 효율(>20%)로 인하여 모듈 크기를 50% 이상 줄임과 동시에 경량화를 이룰 수 있어 비행기, 위성등 탑재체의 에너지 절감에 크게 기여할 수 있다. 고전력용 GaN 전력 스위칭 소자는 기존 Si-기반 IGBT에 비하여 스위칭 손실과 온-저항 손실이 낮아 30% 이상의 에너지 절감이 가능하다. 뿐만 아니라, 일본 도요타 자동차사의 보고에 의하면 HEV등 전기자동차의 DC-DC 부스터 컨버터나 DC-AC 인버터에 GaN 전력반도체를 적용할 경우 경량화, 변환효율 향상, 전용 냉각시스템을 제거할 수 있어 연료소모를 10% 이상 줄일 수 있어 연간 400불 이상의 에너지 절감 효과를 가진다. 이러한 에너지절감 효과는 미국, 유럽, 일본등 선진국을 중심으로 차세대 GaN 반도체의 신시장 개척과 선진입을 위한 치열한 경쟁 구도의 구동력이 될 것이며, 본 논문을 통하여 GaN 반도체의 연구개발 방향과 상용화의 중요성을 함께 생각해보고자 한다.

• Journal of the Korean Vacuum Society
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• v.21 no.3
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• pp.121-129
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• 2012

RF biased inductively coupled plasma (ICP) is widely used in semiconductor and display etch processes which are based on vacuum science. Up to now, researches on how rf-bias power affects have been focused on the controls of dc self-bias voltages. But, effect of RF bias on plasma parameters which give a crucial role in the processing result and device performance has been little studied. In this work, we studied the correlation between the RF bias and plasma parameters and the recent published results were included in this paper. Plasma density was changed with the RF bias power and this variation can be explained by simple global model. As the RF bias was applied to the ICP, increase in the electron temperature from the electron energy distribution was measured indicating electron heating. Plasma density uniformity was enhanced with the RF bias power. This study can be helpful for the control of the optimum discharge condition, as well as the basic understanding for correlation between the RF bias and plasma parameters.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.3 s.36
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• pp.197-205
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• 2005

Development of the packaging is one of the critical issues for commercialization of the RF-MEMS devices. RF MEMS package should be designed to have small size, hermetic protection, good RF performance and high reliability. In addition, packaging should be conducted at sufficiently low temperature. In this paper, a low temperature hermetic wafer level packaging scheme for the RF-MEMS devices is presented. For hermetic sealing, Au-Sn eutectic bonding technology at the temperature below $300{\times}C$ is used. Au-Sn multilayer metallization with a square loop of $70{\mu}m$ in width is performed. The electrical feed-through is achieved by the vertical through-hole via filled with electroplated Cu. The size of the MEMS Package is $1mm\times1mm\times700{\mu}m$. By applying $O_2$ plasma ashing and fabrication process optimization, we can achieve the void-free structure within the bonding interface as well as via hole. The shear strength and hermeticity of the package satisfy the requirements of MIL-STD-883F. Any organic gases or contamination are not observed inside the package. The total insertion loss for the packaging is 0.075 dB at 2 GHz. Furthermore, the robustness of the package is demonstrated by observing no performance degradation and physical damage of the package after several reliability tests.