• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.3
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• pp.685-690
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• 2013

This paper has proposed a multi-channel and wide gain-range baseband circuit blocks for the IEEE 802.15.4g MR-OFDM SUN systems. The proposed baseband circuit blocks consist of two negative-feedback VGAs, an active-RC 5th-order chebyshev low-pass-filter, and a DC-offset cancellation circuit. The proposed baseband circuit blocks provide 1 dB cut-off frequencies of 100 kHz, 200 kHz, 400 kHz, and 600 kHz respectively, and achieve a wide gain-range of +7 dB~+84 dB with 1 dB step. In addition, a DC-offset cancellation circuit has been adopted to mitigate DC-offset problems in direct-conversion receiver. Simulation results show a maximum input differential voltage of $1.5V_{pp}$ and noise figure of 42 dB and 37.6 dB at 5 kHz and 500 kHz, respectively. The proposed I-and Q-path baseband circuits have been implemented in $0.18-{\mu}m$ CMOS technology and consume 17 mW from a 1.8 V supply voltage.

• 전자공학회논문지 IE
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• v.43 no.4
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• pp.28-36
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• 2006

In this paper, an algorithm to classify the 4 motions of arm and a control system to position control the prosthesis are studied. To classify the 4 motions, we use flex sensors which is electrical resistance type sensor that can measure warp of muscle. The flex sensors are attached to the biceps brchii muscle and coracobrachialis muscle and the sensor signals are passed the sensing system. 4 motion of the forearm - flexion and extension, the pronation and supination are classified from this. Also position of forearm is measured from the classified signals. Finally, A two D.O.F prosthesis arm with RC servo-motor is designed to verify the validity of the algorithm. At this time, fuzzy controller is used to reduce the position error by rotary inertia and noise. From the experiment, the position error had occurred within about 5 degree.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.51-59
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• 2009

This paper presents the design of continuous-time sigma-delta modulator for acoustic sensor. The feedforward structure without summing block is used to reduce power consumption of sigma-delta modulator. A high-linearity active-RC filter is used to improve resolution of sigma-delta modulator. Excess loop delay problem in conventional continuous-time sigma-delta modulators is solved by our proposed architecture. A low power, high resolution fourth-order continuous-time sigma-delta modulator with 1-bit quantization was realized in a 0.13-${\mu}m$ 1-Poly 8-metal CMOS technology, with a core area of $0.58\;mm^2$. Simulation results show that the modulator achieves 91.3-dB SNR over a 25-kHz signal bandwidth with an oversampling ratio of 64, while dissipating $290{\mu}W$ from a 3.3-V supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.158-165
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• 2013

In this paper, a new circuit topology of an ultra-wideband (UWB) 3.1-10.6GHz CMOS low noise amplifier is presented. The proposed UWB low noise amplifier is designed utilizing RC feedback and LC filter networks which can provide good input impedance matching. In this design, the current-reused topology is adopted to reduce the power consumption and the inductor-peaking technique is applied for the purpose of bandwidth extension. The performance results of this UWB low noise amplifier simulated in $0.18-{\mu}m$ CMOS process technology exhibit a power gain of 14-14.9dB, an input matching of better than -10.8dB, gain flatness of 0.9dB, and a noise figure of 2.7-3.3dB in the frequency range of 3.1-10.6GHz. In addition, the input IP3 is -5dBm and the power consumption is 12.5mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.8
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• pp.1536-1547
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• 1994

This paper presented the implementation and design of narrowband wireless MODEM for packet transmission. The MODEM consists of transmitter, receiver, and the control unit. The BPSK modulation with narrowband filtering is used. The receiver consists of functional modules such as carrier recovery, bit synchronization, lock detector, etc. We evaluated the performance of packet transmission with three MODEM sets implemented in distributed packet radio network. We confirmed the transmission of packetized data through RS232C port of PC. Also, we presented results of experimental data by using measuring instruments. The implemented MODEM in this paper is expected to be useful for the design of wireless LAN system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.1
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• pp.47-55
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• 2005

This work describes an 8b 240 MS/s CMOS ADC as one of embedded core cells for high-performance displays requiring low power and small size at high speed. The proposed ADC uses externally connected pins only for analog inputs, digital outputs, and supplies. The ADC employs (1) a two-step pipelined architecture to optimize power and chip size at the target sampling frequency of 240 MHz, (2) advanced bootstrapping techniques to achieve high signal bandwidth in the input SHA, and (3) RC filter-based on-chip I/V references to improve noise performance with a power-off function added for portable applications. The prototype ADC is implemented in a 0.18 um CMOS and simultaneously integrated in a DVD system with dual-mode inputs. The measured DNL and INL are within 0.49 LSB and 0.69 LSB, respectively. The prototype ADC shows the SFDR of 53 dB for a 10 MHz input sinewave at 240 MS/s while maintaining the SNDR exceeding 38 dB and the SFDR exceeding 50 dB for input frequencies up to the Nyquist frequency at 240 MS/s. The ADC consumes, 104 mW at 240 MS/s and the active die area is 1.36 ㎟.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.4
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• pp.333-340
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• 2011

KJJVC(Korea-Japan Joint VLBI Correlator) was installed at the KJCC(Korea-Japan Correlation Center) and has been operated by KASI(Korea Astronomy and Space Science Institute) from 2009. KJNC is able to correlate the VLBI observed data through KVN(Korean VLBI Network), VERA(VLBI Exploration of Radio Astrometry), and JVN(Japanese VLBI Network) and its joint network array. And it is used exclusively as computer in order to process the observed data for the scientific purpose KJJVC used the VSI(VLBI Standard Interface) as the VLBI international standard at the data input-output specification between each component. Especially, for correlating the observed data, the data is transmitted with 1024Mbps speed between Mark5B high-speed playback and RVDB(Raw VLBI Data Buffer). The EMI(Electromagnetic lnterference), which is occurred by data transmission with high-speed, cause the data loss and the loss occurrence is frequently often for long transmission cable. Finally it will be caused the data recognition error by decreasing the voltage level of digital data signal. In this paper, in order to minimize the data loss by measuring the EMI noise level in transmission of the VSI specification, the 3 methods such as 1) RC filtering method, 2) lmpedance matching using Microstrip line, and 3) Signal buffering method using Differential line driver, were proposed. To verify the effectiveness of each proposed method, the performance evaluation was conducted by implementing and simulations for each method. Each proposed method was effectively confirmed as the high-speed data transmission of the VSI specification.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.225-228
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• 2012

In this paper, a 10-bit digital-to-analog converter (DAC) with small area is proposed. The 10-bit DAC consists of a 8-bit decoder, a 2-bit time-interpolator, and a buffer amplifier. The proposed time-interpolation is achieved by controlling the charging time through a low-pass filter composed of a resistor and a capacitor. To implement the accurate time-interpolator, a control pulse generator using a replica circuit is proposed to minimize the effect of the process variation. The proposed 10-bit Time-Interpolation DAC occupies 61 % of the conventional 10-bit resistor-string DAC. The proposed DAC is designed using a $0.35{\mu}m$ CMOS process with a 3.3 V supply. The simulated DNL and INL are +0.15/-0.21 LSB and +0.15/-0.16 LSB, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.