• Journal of the Korea Institute of Information Security & Cryptology
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• v.27 no.3
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• pp.449-457
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• 2017

In this paper, we analyze the security and performance of the Quantis Quantum random number generator in terms of cryptography through experiments. The Quantis' post-processing is designed to output full-entropy via bit-matrix-vector multiplication based on mathematical background, and we used the min-entropy estimating test of NIST SP 800-90B so as to verify whether the output is full-entropy. Quantis minimizes the effect on the random bit rate by using an optimization technique for bit-matrix-vector multiplication, and compared the performance to conditioning functions of NIST SP 800-90B by measuring the random bit rate. Also, we have distinguished what is in Quantis' post-processing to the standard model of NIST in USA and BSI in Germany, and in case of applying Quantis to cryptographic systems in accordance with the CMVP standard, it is recommended to use the output of Quantis as the seed of the approved DRBG.

• ETRI Journal
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• v.45 no.3
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• pp.365-378
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• 2023

ARIA is a block cipher proposed by Kwon et al. at ICISC 2003 that is widely used as the national standard block cipher in the Republic of Korea. Herein, we identify some flaws in the quantum rebound attack on seven-round ARIA-DM proposed by Dou et al. and reveal that the limit of this attack is up to five rounds. Our revised attack applies to not only ARIA-DM but also ARIA-MMO and ARIA-MP among the PGV models, and it is valid for all ARIA key lengths. Furthermore, we present dedicated quantum rebound attacks on seven-round ARIA-Hirose and ARIA-MJH for the first time. These attacks are only valid for the 256-bit key length of ARIA because they are constructed using the degrees of freedom in the key schedule. All our attacks are faster than the generic quantum attack in the cost metric of the time-space tradeoff.

• ETRI Journal
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• v.45 no.3
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• pp.534-542
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• 2023

The large amount of secondary effects in complementary metal-oxide-semiconductor technology limits its application in the ultra-nanoscale region. Circuit designers explore a new technology for the ultra-nanoscale region, which is the quantum-dot cellular automata (QCA). Low-energy dissipation, high speed, and area efficiency are the key features of the QCA technology. This research proposes a novel, low-complexity, QCA-based one-bit digital comparator circuit for the ultra-nanoscale region. The performance of the proposed comparator circuit is presented in detail in this paper and compared with that of existing designs. The proposed QCA structure for the comparator circuit only consists of 19 QCA cells with two clock phases. QCA Designer-E and QCA Pro tools are applied to estimate the total energy dissipation. The proposed comparator saves 24.00% QCA cells, 25.00% cell area, 37.50% layout cost, and 78.11% energy dissipation compared with the best reported similar design.

• 한국초전도학회:학술대회논문집
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• v.13
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• pp.53-53
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• 2003

• 한국초전도학회:학술대회논문집
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• v.15
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• pp.46-46
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• 2005

• Progress in Superconductivity
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• v.8 no.2
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• pp.181-185
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• 2007

For more than two decades Nb trilayer ($Nb/Al_2O_3/Nb$) process has been serving as the most stable fabrication process of the Josephson junction integrated circuits. Fast development of semiconductor fabrication technology has been possible with the recent advancement of the fabrication equipments. In this work, we took an advantage of advanced fabrication equipments in developing a superconducting Arithmetic Logic Unit (ALU) by using Nb trilayers. The ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We used DC magnetron sputtering technique for metal depositions and RF sputtering technique for $SiO_2$ depositions. Various dry etching techniques were used to define the Josephson junction areas and film pattering processes. Our Nb films were stress free and showed the $T{_c}'s$ of about 9 K. To enhance the step coverage of Nb films we used reverse bias powered DC magnetron sputtering technique. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. Our 1-bit ALU operated correctly at up to 40 GHz clock frequency, and the 4-bit ALU operated at up to 5 GHz clock frequency.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.1
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• pp.73-83
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• 2018

There has been increasing interest from NIST and other companies in studying post-quantum cryptography in order to resist against quantum computers. Multivariate polynomial based, code based, lattice based, hash based digital signature, and isogeny based cryptosystems are one of the main categories in post quantum cryptography. Among these categories, isogeny based cryptosystem is known to have shortest key length. In this paper, we implemented Supersingular Isogeny Diffie-Hellman (SIDH) protocol efficiently on low-end mobile device. Considering the device's specification, we select supersingular curve on 523 bit prime field, and generate efficient isogeny computation tree. Our implementation of SIDH module is targeted for 32bit environment.

• Progress in Superconductivity
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• v.5 no.1
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• pp.21-25
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• 2003

We have designed and simulated an 1-bit ALU (Arithmetic Logic Unit) by using a half adder. An ALU is the part of a computer processor that carries out arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We constructed an 1-bit ALU by using only one half adder and three control switches. We designed the control switches in two ways, dc switch and NDRO (Non Destructive Read Out) switch. We used dc switches because they were simple to use. NDRO pulse switches were used because they can be easily controlled by control signals of SET and RESET and show fast response time. The simulation results showed that designed circuits operate correctly and the circuit minimum margins were ＋/-27%. In this work, we used simulation tools of XIC and WRSPICE. The circuit layouts were also performed. The circuits are being fabricated.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.902-905
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• 2004

A heart diagnosis system adopts Superconducting Quantum Interface Device(SQUID) sensors for precision MCG signal acquisitions. Such system is composed of hundreds of sensors, requiring fast signal sampling and precise analog-digital conversions(ADC). Our development of hardware board, processing 64-channel 12-bit 1ks/s, is built by using 8-channel ADC chips, 8-bit microprocessors, SPI interfaces, and parallel data transfers between microprocessors to meet the 1ks/s, i.e. 1 ms speed. The test result shows that the signal acquisition is done in 168 usuc which is much shorter than the required 1 ms period. This hardware will be extended to 256 channel data acquisition to be used for the diagnosis system.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.10a
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• pp.117-119
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• 2003

We have designed fabricated, and tested an RSFQ(Rapid Single Flux Quantum) 1-bit ALU (Arithmetic Logic Unit). The 1-bit ALU was composed of a half adder and three SFQ DC switches. Three DC switches were attached to the two output ports of an ALU for the selection of each function from the available functions that were AND, OR, XOR and ADD. And we also attached two DC switches at the input ports of the half adder so that the input data were controlled using the function generators operating at low speed while we tested the circuit at high speed. The test bandwidth was from 1KHz to 5 ㎓. The chip was tested at the liquid helium temperature of 4.2 K.