• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2016.05a
• /
• pp.367-370
• /
• 2016

QFN(Quad Flat No-leads package) is one of the SMD(Surface Mount Device). Since there is no lead in QFN, there are many defects on solder. Therefore, we propose an efficient mechanism for QFN solder defect detection at this paper. For this, we employ Convolutional Neural Network(CNN) of the Machine Learning algorithm. QFN solder's color multi-layer images are used to train CNN. Since these images are 3-channel color images, they have a problem with applying to CNN. To solve this problem, we used each 1-channel grayscale image(Red, Blue, Green) that was separated from 3-channel color images. We were able to detect QFN solder defects by using this CNN. Later, further research is needed to detect other QFN.

• Journal of the Semiconductor & Display Technology
• /
• v.15 no.3
• /
• pp.18-23
• /
• 2016

QFN (Quad Flat No-leads Package) is one of the SMD (Surface Mount Device). Since there is no lead in QFN, there are many defects on solder. Therefore, we propose an efficient mechanism for QFN solder defect detection at this paper. For this, we employ Convolutional Neural Network (CNN) of the Machine Learning algorithm. QFN solder's color multi-layer images are used to train CNN. Since these images are 3-channel color images, they have a problem with applying to CNN. To solve this problem, we used each 1-channel grayscale image (Red, Green, Blue) that was separated from 3-channel color images. We were able to detect QFN solder defects by using this CNN. In this paper, it is shown that the CNN is superior to the conventional multi-layer neural networks in detecting QFN solder defects. Later, further research is needed to detect other QFN.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2012.10a
• /
• pp.343-344
• /
• 2012

• Journal of Institute of Control, Robotics and Systems
• /
• v.15 no.9
• /
• pp.899-905
• /
• 2009

There are many different types of surface defects on semiconductor Integrated Chips (IC's) caused by various factors during manufacturing process, such as Scratch, Flash, Resin bleed, and Melting. These defects must be detected and classified by an inspection system for productivity improvement and effective process control. Among defects, in particular, Resin bleed and Melting are the most difficult ones to classify accurately. The brightness value and the shape of Resin bleed and Melting defects are so similar that normally it is difficult to classify the Resin bleed and Melting. In this paper, we propose a segmenting method and a set of features for detecting and classifying the Resin bleed and Melting defects.

• Journal of the Institute of Convergence Signal Processing
• /
• v.10 no.2
• /
• pp.120-126
• /
• 2009

There are many different types of surface defects on semiconductor Integrated Chips (IC's) caused by various factors during manufacturing process, such as cracks, foreign materials, chip-outs, chips, and voids. These defects must be detected and classified by an inspection system for productivity improvement and effective process control. Among defects, in particular, foreign materials and chips are the most difficult ones to classify accurately. A vision system composed of a carefully designed optical system and a processing algorithm is proposed to detect and classify the defects on QFN(Quad Flat No-leads) packages. The processing algorithm uses features derived from the defect's position and brightness value in the Maximum Likelihood classifier and the optical system is designed to effectively extract the features used in the classifier. In experiments we confirm that this method gives more effective result in classifying foreign materials and chips.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.2
• /
• pp.301-306
• /
• 2015

An ultra-compact and wideband low noise amplifier (LNA) in a quad flat non-leaded (QFN) package is presented. The LNA monolithic microwave integrated circuit (MMIC) is implemented in a $0.25{\mu}m$ GaN IC technology on a Silicon Carbide (SiC) substrate provided by Triquint. A source degeneration inductor and a gate inductor are used to obtain the noise and input matching simultaneously. The resistive feedback and inductor peaking techniques are employed to achieve a wideband characteristic. The LNA chip is mounted in the $3{\times}3-mm^2$ QFN package and measured. The supply voltages for the first and second stages are 14 V and 7 V, respectively, and the total current is 70 mA. The highest gain is 13.5 dB around the mid-band, and -3 dB frequencies are observed at 0.7 and 12 GHz. Input and output return losses ($S_{11}$ and $S_{22}$) of less than -10 dB measure from 1 to 12 GHz; there is an absolute bandwidth of 11 GHz and a fractional bandwidth of 169%. Across the bandwidth, the noise figures (NFs) are between 3 and 5 dB, while the output-referred third-order intercept points (OIP3s) are between 26 and 28 dBm. The overall chip size with all bonding pads is $1.1{\times}0.9mm^2$. To the best of our knowledge, this LNA shows the best figure-of-merit (FoM) compared with other published GaN LNAs with the same gate length.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.40 no.12
• /
• pp.2503-2510
• /
• 2015

This paper presents a single-phase energy measurement IC to measure electric power quantities. The entire IC includes two programmable gain amplifiers (PGAs), two ${\sum}{\Delta}$ modulators, a reference circuit, a low-dropout (LDO) regulator, a temperature sensor, a filter unit, a computation engine, a calibration control unit, registers, and an external interface block. The proposed energy measurement IC is fabricated with $0.18-{\mu}m$ CMOS technology and housed in a 32-pin quad-flat no-leads (QFN) package. It operates at a clock speed of 4,096 kHz and consumes 10 mW in 3.3 V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.27 no.2
• /
• pp.108-114
• /
• 2016

This paper presents a 2.6 GHz Doherty power amplifier IC to enhance the back-off efficiency. In order to apply to small-cell base stations, the Doherty power amplifier was fabricated using GaN-HEMT process for high power density. In addition, the implemented Doherty power amplifier was mounted on a QFN package. The implemented GaN-HEMT Doherty power amplifier was measured using LTE downlink signal with 10 MHz bandwidth and 6.5 dB PAPR for verification. A power gain of 15.8 dB, a drain efficiency of 43.0 %, and an ACLR of -30.0 dBc were obtained at an average output power level of 33.9 dBm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.29 no.5
• /
• pp.336-343
• /
• 2018

We herein present the design and fabrication of a Rx core chip operating in the X-band (10.5~13 GHz) using Win's commercial $0.25-{\mu}m$ GaAs pHEMT process technology. The X-band core chip comprises a low-noise amplifier, a four-bit phase shifter, and a serial-to-parallel data converter. The size is $1.75mm{\times}1.75mm$, which is the state-of-the-art size. The gain and noise figure are more than 10 dB but less than 2 dB, and both the input and output return losses are less than 10 dB. The RMS phase error is less than $5^{\circ}$, and the P1dB is 2 dBm at 12.5 GHz, the performance of which is equivalent to other GaAs core chips. The fabricated core chip was packaged in a QFN package type with a size of $3mm{\times}3mm$ for the convenience of assembly. We confirmed that the performance of the packaged core chip was almost the same as that of the chip itself.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.24 no.6
• /
• pp.633-643
• /
• 2013

GDS format files, as well as layout of the chip are noticeably needed so as to analyze the PDN (Power Delivery Network) inside of IC; however, commercial IC in the market has not supported design information which is layout of IC. Within this, in terms of IC having on-chip PDN, characteristic of inside PDN of the chip is a core parameter to predict generated noise from power/ground planes. Consequently, there is a need to scrutinize extraction method for unknown PDN of the chip in this paper. To extract PDN of the chip without IC circuit information, the de-embedding test vehicle is fabricated based on IEC62014-3. Further more, the extracted inside PDN of chip from de-embedding technique adopts the Co-simulation model which composes PCB, QFN (Quad-FlatNo-leads) Package, and Chip for the PDN, applied Co-simulation model well corresponds with impedance from measured S-parameters up to 4 GHz at common measured and simulated points.