• The KIPS Transactions:PartB
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• v.9B no.6
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• pp.715-726
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• 2002

In this paper, we construct real-time moving picture encoder based on fractal theory by using general purpose digital signal processors. The constructed encoder is implemented using two fixed-point general DSPs (ADSP2181) and performs image encoding by three stage pipeline structure. In the first pipeline stage, the image grabber acquires image data from NTSC standard image signals and stores digital image into frame memory. In the second stage, the main controller encode image dada using fractal algorithm. The last stage, output controller perform Huffman coding and result the coded data via RS422 port. The performance tests of the constructed encoder shows over 10 frames/sec encoding speed for QCIF data when all the frames are encoded. When we encode the images using the interframe and redundency based on the proposed algorithms, encoding speed increased over 30 frames/sec in average.

• The Journal of the Korea Contents Association
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• v.9 no.2
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• pp.1-9
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• 2009

In this paper, we propose the efficient processing technique for unavailable data in hardware implementation of motion estimator in H.264/AVC with parallel processing architecture. Motion estimation processing in the hardware is generally based on pipe-lining, some MV data of neighbor blocks are not available, whereas all MV data are valid in software processing where the data are sequentially processed. In this paper, we solve the problem of data being unavailable in MVp computation. To minimize the quality degradation caused by unavailable MVs, in the proposed method, the unavailable MV of a neighboring block is replaced with an integer pel unit MV, an MVp of neighboring blocks, or an MVcol (MV of co-located block). Comparing to the conventional method [7], our method outperformed maximally 0.832dB and 0.179dB for QCIF and CIF, respectively, in terms of BDPSNR.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.71-78
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• 2008

In this paper, we implement the H.264/AVC baseline decoder by hardware-software partitioning under the embedded Linux Kernel 2.4.26 and the FPGA-based target board with ARM926EJ-S core. We design several IPs for the time-demanding blocks, such as motion compensation, deblocking filter, and YUV-to-RGB and they are communicated with the host through the AMBA bus protocol. We also try to minimize the number of memory accesses between IPs and the reference software (JM 11.0) which is ported in the embedded Linux. The proposed IPs and the system have been designed and verified in several stages. The proposed system decodes the QCIF sample video at 2 frame per second when 24MHz of system clock is running and we expect the bitter performance if the proposed system is designed with ASIC.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.8
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• pp.1675-1685
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• 2012

DVC (Distributed Video Coding) technique plays an essential role in providing low-complexity video encoder. But, in order to achieve the better rate-distortion performances, most DVC systems need feedback channel for parity bit control. This causes the DVC-based system to have high decoding latency and becomes as one of the most critical problems to overcome for a real implementation. In order to overcome this problem and to accelerate the commercialization of the DVC applications, this paper analyzes an effect of LDPCA frame size for adaptive LDPCA frame-based parity bit request estimations. First, this paper presents the LDPCA segmentation method in pixel-domain and explains the temporal-based bit request estimation method and the spatial-based bit request estimation method using the statistical characteristics between adjacent LDPCA frames. Through computer simulations, it is shown that the better performance and fast decoding is observed specially when the LDPCA frame size is 3168 in QCIF resolution.

• Journal of Broadcast Engineering
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• v.16 no.1
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• pp.144-154
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• 2011

In this paper, we propose a parallel LDPCA encoding method for fast transform-domain Wyner-Ziv video encoding which is suitable in an ultra fast and low power video encoding. The conventional transform-domain Wyner-Ziv video encoding performs LDPCA channel coding of quantized transform coefficients in bitplane-serial fashion, which takes about 60% of total encoding time, and this computational complexity becomes severer as the bitrate increases. The proposed method binds several bitplanes into one packed message and carries out the LDPCA encoding in parallel. The proposed LDPCA encoding method improves the encoding speed by 8 ~ 55 times. In the experiment, the proposed Wyner-Ziv encoder can encode 700 ~ 2,300 QCIF size frames per second with GOP=64. The method can be applied to the pixel-domain Wyner-Ziv encoder using LDPCA, and has a wide scope of application.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.31-43
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• 1999

The main goal of this paper is to design a high performance SVP(Stack based Video Processor) for network applications. The SVP is a comprehensive scheme; 'better' in the sense that it is an optimal selection of previously proposed enhancements of a stack machine and a video processor. This can process effectively object-based video data using a S-RISC(Stack-based Reduced Instruction Set Computer) with a semi -general-purpose architecture having a stack buffer for OOP(Object-Oriented Programming) with many small procedures at running programs. And it includes a vector processor that can improve the MPEG coding speed. The vector processor in the SVP can execute advanced mode motion compensation, motion prediction by half pixel and SA-DCT(Shape Adaptive-Discrete Cosine Transform) of MPEG-4. Absolutors and halfers in the vector processor make this architecture extensive to a encoder. We also designed a VLSI stack-oriented video processor using the proposed architecture of stack-oriented video decoding. It was designed with O.5$\mu\textrm{m}$ 3LM standard-cell technology, and has 110K logic gates and 12 Kbits SRAM internal buffer. The operating frequency is 50MHz. This executes algorithms of video decoding for QCIF 15fps(frame per second), maximum rate of VLBV(Very Low Bitrate Video) in MPEG-4.

• The KIPS Transactions:PartB
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• v.10B no.2
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• pp.189-196
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• 2003

This paper describes an error resilient video data transmission method using information hiding. In order to localize transmission errors in receiver, video encoder embeds one bit for a macro block during encoding process. Embedded information is detected during decoding process in the receiver, and the transmission errors can be localized by comparing the original embedding data. The localized transmission errors can be easily corrected, thus the degradation in a reconstructed image can be alleviated. Futhermore, the embedded information can be applied to protect intellectual property rights of the video data. Experimental results for 3 QCIF sized video sequenced composed of 150 frames respectively show that, while degradation in video streams in which the information is embedded is negligible, especially in a noisy channel, the average PSNR of reconstructed images can be improved about 5 dB by using embedded information. Also, intellectual property rights information can be effectively obtained from reconstructed images.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.8C
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• pp.790-800
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• 2009

For the improvement of coding efficiency, the H.264/AYC standard uses new coding tools such as 1/4-pel-accurate motion estimation, multiple references, intra prediction, loop filter, variable block size etc. Using these coding tools, H.264/AYC has achieved significant improvements from rate-distortion point of view compared to existing standards. However, the encoder complexity was greatly increased due to these coding tools. We focus on the complexity reduction method of intra macroblock mode selection. The proposed algorithm for fast intra mode selection calculates the edge activity in transform domain, and performs fast encoding of intra frame in H.264/AYC through the fast prediction mode selection of intra4x4 and chrominance blocks. Simulation results show that the proposed method saves about 59.76% for QCIF sequences and 65.03% for CIF sequences of total encoding time, while bitrate increase and PSNR decrease are very small.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.1
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• pp.157-164
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• 2012

This paper introduces an implementation of SVC player which runs on Android platform and can play SVC video stream on line from SVC video server. SVC(Scalable Video Coding) is a scalable video encoding technique which supports three scalability such as temporal scalability, spatial scalability, and quality scalability. To implement the SVC player on Android, we implemented a SVC decoder using JSVM open source written in C/C++ as a native part on Android and developed Android UI in Java. Also we built an SVC encoding system off line and an SVC streaming server to conduct on-line SVC streaming experiments. Finally, after we installed the SVC player developed in this paper on Motoroi mobile phone, we evaluated and analyzed on-line streaming performance of the SVC player. The result showed that the player worked well and it had no jitter in streaming with the size of QCIF and 10fps from a fully encoded SVC video source.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.5
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• pp.477-485
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• 2002

In this paper, we present an efficient hardware architecture for the H.263 video codec and its VLSI implementation. This architecture is based on the unified interface by which internal hardware engines and an internal RISC processor are connected one another. The unified interface enables the modular design of internal blocks, efficient hardware/software partitioning, and pipelined paralled operations. The developed VLSI supports the H.263 version 2 profile 3 @ level 10, and moreover, both the control protocol H.245 and the multiplexing protocol H.223. Therefore, it can be used for the complete ITU-T H.324 or 3GPP 3G 324M multimedia processor with the help of an external audio codec. Simultaneous encoding and decoding of QCIF format images at a rate greater than 15 frames per second is achieved at 40 MHz clock frequency.