• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
• /
• pp.83-85
• /
• 2007

A new approach on identifying a first-order plus time-delay (FOPTD) model using finite--duration pulse inputs has been presented recently [1]. The identification methods are very simple because it is enough to observe only two extremes and the time when they occur in the transient response to pulse input. However, when there is mismatch between actual system and FOPTD model. how sensitive the methods are has not been studied. In this paper, we investigate robustness issue of those identification algorithms in the presence of the model structure mismatch and uncertainties. Through an example we will demonstrate it.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2003년도 하계학술대회 논문집 C
• /
• pp.1852-1854
• /
• 2003

In manufacturing processes, various and suitable pulse shapes are required for the purpose of material processing. In order to make various pulse shapes with variable pulse length and high duty cycle, We have fabricated the power supply consisting 6 SCRs and the Pulse Forming Network(PFN) with the precise delay time control. So our control system has three switching circuits, 3 mesh PFN, and simmer circuit. In addition, we have designed and fabricated the PIC one-chip microprocessor(16F877) to control the delay time of sequential switching.

• 한국광학회지
• /
• 제2권4호
• /
• pp.197-202
• /
• 1991

극초단 레이저 펄스의 펄스폭(pulse width)을 측정하기 위하여 SHG방법을 이용한 실시간(real time) 자기상관계(autocorrelator)를 개발하였다. 본 연구에서 개발한 자기상관계의 측정법위는 142 ps이며, 지연(delay) block을 한쪽 arm에 삽입하면 250ps까지 측정범위가 확장된다. CW mode-locked Nd:YLF 레이저의 공진기 길이가 mode-locker의 RF 주파수와 matching 되었을 때 가장 짧은 20ps의 펄스폭을 측정하였으며, 공진기 길이를 detuning함에 따란 39ps와 47ps의 펄스폭을 측정 하였다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2003년도 하계종합학술대회 논문집 Ⅳ
• /
• pp.2427-2430
• /
• 2003

A uniformly sampled digital pulse-width modulation adopting a pre-compensation filter scheme for applications in high-resolution digital-to-analog data conversion is described. It is shown that linearization of the intrinsic distortion resulting in uniformly sampled pulse-width modulation can be achieved by using a non-integer delay digital filter embedded within a noise shaping re-quantizer.

• 한국광학회지
• /
• 제29권1호
• /
• pp.1-6
• /
• 2018

본 연구에서는 광선추적 소프트웨어를 이용하여 광학계의 광경로를 계산한 후, 이를 이용하여 위상, 그룹지연(GD), 그룹지연분산(GDD), 그리고 3차지연분산(TOD)를 계산하였다. 프리즘 쌍과 회절격자 쌍을 이용한 펄스 압축기를 설계하였으며, 실제 펨토초 광섬유 레이저의 GDD를 0으로 보정하는 펄스 압축기를 전산시늉하였다. 또한, 회절격자 쌍과 렌즈 쌍, 혹은 거울 쌍을 이용한 펄스 확장기를 설계하였다. 본 연구 결과는 광학계의 분산특성 계산과 극초단 펄스 레이저 광학계의 성능 향상에 활용할 수 있다.

• 한국산업정보학회논문지
• /
• 제20권1호
• /
• pp.1-7
• /
• 2015

In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration has been proposed for digital controlled DC-DC converters. The hybrid structure of DPWM combines a 6-bit differential tapped delay line ring-mux digital-to-time converter (DTC) schema and a 6-bit counter-comparator DTC schema, resulting in a power and area saving solution. Furthermore, since the 6-bit differential delay line ring oscillator serves as the clock to the high 6-bit counter-comparator DTC, a high frequency clock is eliminated, and the power is significantly saved. In order to have a simple delay cell and flexible delay time controllability, a voltage controlled inverter is adopted to build the deferential delay cell, which allows fine-tuning of the delay time. The PT calibration circuit is composed of process and temperature monitors, two 2-bit flash ADCs and a lookup table. The monitor circuits sense the PT (Process and Temperature) variations, and the flash ADC converts the data into a digital code. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.

• Journal of information and communication convergence engineering
• /
• 제2권2호
• /
• pp.102-105
• /
• 2004

A Quadrature phase detector for high-speed delay-locked loop is introduced. The proposed Quadrature phase detector is composed of two nor gates and it determines if the phase difference of two input clocks is 90 degrees or not. The delay locked loop circuit including the Quadrature phase detector is fabricated in a 0.18 um Standard CMOS process and it operates at 5 GHz frequency. The phase error of the delay-locked loop is maximum 2 degrees and the circuits are robust with voltage, temperature variations.

• 한국군사과학기술학회지
• /
• 제14권1호
• /
• pp.114-122
• /
• 2011

In this paper, we have identified the system instability factors in a bistatic radar system using pulse chasing and considered their effects on the bistatic receiver's MTI(Moving Target Indication) improvement performance. The pulse chasing is a method to efficiently scan a restricted search area within the limited transmitter power and time in a bistatic radar and to track a series of transmitted pulses using the receiver beam which has ideally matched to the pulse propagation rate. In this paper, we have discussed the interrelationship between the pulse chasing and time and frequency/phase synchronization and described the effects of the identified system instability factors on two kinds of MTI filter configuration, single delay-line and double delay-line, in the bistatic radar. And also, we have confirmed that the overall system improvement is restricted by a lower improvement factor among identified them, and discussed the allowable tolerance of the time and frequency/phase synchronization in the bistatic system.

• 한국항공우주학회지
• /
• 제39권9호
• /
• pp.889-895
• /
• 2011

최신의 항공기는 상대 항공기의 레이더에 검출되지 않기 위해 다양한 방법을 적용하고 있다. 레이더를 통해 감지가 어려운 적기의 존재 유무를 파악하고 적기와의 상대적인 거리 차이와 방위를 추정하기 위해 레이더 경보 수신기(RWR, Radar Warning Receiver)가 이용될 수 있다. 기존의 레이더 경보 수신기는 도달 각(AOA, Angle Of Arrival)을 구하고, 도달 각의 방향성으로 레이더 펄스가 발산된 위치를 추정하였다. 따라서 보다 정확한 위치를 추정하기 위해서 보다 정확한 도달 각을 구하는데 초점을 두었다. 반면 도달 각을 정확하게 구하더라도 레이더 펄스를 발산한 상대 항공기가 빠른 속도로 이동하는 경우 정확한 위치 추정은 어렵다. 본 논문에서는 레이더 펄스가 발산된 정확한 위치를 추정하기 위하여, 초고주파의 레이더 펄스 신호에서 저주파수 신호의 위상지연차를 이용하여, 관심 영역에 대한 스캐닝 기법으로 레이더 펄스가 발산된 위치를 추정하였다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제6권2호
• /
• pp.74-78
• /
• 2006

This paper presents a high-speed pulse-based flip-flop with pseudo MUX-type scan compatible with the conventional master-slave flip-flop with MUX-type scan. The proposed flip-flop was implemented as the standard cell library using Samsung 130nm HS technology. The data-to-output delay and power-delay-product of the proposed flip-flop are reduced by up to 59% and 49%, respectively. By using this flop-flop, ARM11 softcore has achieved the maximum 1GHz operating speed.