• The Transactions of the Korean Institute of Power Electronics
• /
• v.21 no.2
• /
• pp.126-133
• /
• 2016

This paper proposes a new PWM method to reduce the common mode voltage change in three-level Vienna rectifier. This new proposed PWM method uses medium voltage vector for the three-level Vienna rectifier to determine the sum of three-phase voltage zero, and the common mode voltage variation is decreased. Using the carrier comparison method, the switching function generator for three-level Vienna rectifier has been proposed. The effects of the proposed PWM method have been verified through simulation using the PSIM.

• Journal of Power Electronics
• /
• v.16 no.1
• /
• pp.142-152
• /
• 2016

Common mode voltage (CMV) generation is a major problem in switching power converter fed induction motor drive systems. CMV is the zero sequence voltage generated due to the switching action of power converters. Even a small magnitude of CMV with a high rate of change may circulate large bearing currents which may damage a machine's bearings and shorten its life. There are several methods of controlling CMV. This paper presents 3-level sinusoidal pulse width modulation based techniques to control the magnitude and rate of change of CMV in multilevel AC-DC-AC drive systems. Simulation and experimental investigations have been presented to validate the performance of proposed technique to control CMV in 3-level neutral point clamped inverter based AC-DC-AC system.

• Journal of Power Electronics
• /
• v.12 no.5
• /
• pp.715-722
• /
• 2012

New discrete time domain models for the peak current controlled (PCC) power LED drivers in continuous conduction mode include for the first time the effects of the time delay in the pulse-width-modulator. Realistic amounts of time delay are found to have significant effects on the average output LED current and on the critical inductor value at the boundary between the two conduction modes. Especially, the time delay can provide an accurate LED current for the PCC buck converter with a wide input voltage. The models can also predict the critical inductor value at the mode boundary as functions of the input voltage and the time delay. The overshoot of the peak inductor current due to the time delay results in the increase of the average output current and the reduction of the critical inductor value at the mode boundary in all converters. Experimental results are presented for the PCC buck LED driver with constant-frequency controller.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.27 no.5
• /
• pp.446-454
• /
• 2022

This study proposes a carrier-based pulse width modulation (PWM) method for leakage current reduction and neutral point (NP) current control in a three-phase three-level converter, which is a carrier-based PWM version of the previously proposed low-frequency common mode voltage PWM. Three groups of space vectors with the same common mode voltage are used. When the averaged NP current needs to be positive or negative, the specific groups are employed to produce low-frequency common mode voltages. The validity of the proposed PWM method is verified through experiments.

• ETRI Journal
• /
• v.39 no.4
• /
• pp.582-591
• /
• 2017

To address the wire complexity problem in large-scale globally asynchronous, locally synchronous systems, a current-mode ternary encoding scheme was devised for a two-phase asynchronous protocol. However, for data transmission through a very long wire, few studies have been conducted on reducing the long propagation delay in current-mode circuits. Hence, this paper proposes a current steering logic (CSL) that is able to minimize the long delay for the devised current-mode ternary encoding scheme. The CSL creates pulse signals that charge or discharge the output signal in advance for a short period of time, and as a result, helps prevent a slack in the current signals. The encoder and decoder circuits employing the CSL are implemented using $0.25-{\mu}m$ CMOS technology. The results of an HSPICE simulation show that the normal and optimal mode operations of the CSL achieve a delay reduction of 11.8% and 28.1%, respectively, when compared to the original scheme for a 10-mm wire. They also reduce the power-delay product by 9.6% and 22.5%, respectively, at a data rate of 100 Mb/s for the same wire length.

• Journal of Power Electronics
• /
• v.14 no.2
• /
• pp.315-323
• /
• 2014

An optimized space vector pulse width modulation (SVPWM) method with common mode voltage elimination and neutral point potential balancing is proposed for an open-end winding induction motor. The motor is fed from both of the ends with two neutral point clamped (NPC) three-level inverters. In order to eliminate the common mode voltage of the motor ends and balance the neutral point potential of the DC link, only zero common mode voltage vectors are used and a balancing control factor is gained from calculation in the strategy. In order to improve the harmonic characteristics of the output voltages and currents, the balancing control factor is regulated properly and the theoretical analysis is provided. Simulation and experimental results show that by adopting the proposed method, the common mode voltage can be completely eliminated, the neutral point potential can be accurately balanced and the harmonic performance for the output voltages and currents can be effectively improved.

• Journal of Power Electronics
• /
• v.10 no.1
• /
• pp.27-33
• /
• 2010

This paper presents a bidirectional DC-DC converter suitable for low-voltage super capacitor-based electric energy storage systems. The DC-DC converter presented here consists of a full-bridge circuit and a current-fed push-pull circuit with a high frequency (HF) transformer-link. In order to reduce the device-conduction losses due to the large current of the super capacitor as well as unnecessary ringing, synchronous rectification is employed in the super capacitor-charging mode. A wide range of voltage regulation between the battery and the super capacitor can be realized by employing a Phase-Shifting (PS) Pulse Width Modulation (PWM) scheme in the full-bridge circuit for the super capacitor charging mode as well as the overlapping PWM scheme of the gate signals to the active power devices in the push-pull circuit for the super capacitor discharging mode. Essential performance of the bidirectional DC-DC converter is demonstrated with simulation and experiment results, and the practical effectiveness of the DC-DC converter is discussed.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.9 no.1
• /
• pp.10-16
• /
• 2004

In this thesis, improved full wave mode ZVT(Zero-Voltage-Transition) PMW DC-DC Converters are presented to maximize the regeneration ratio of resonant energy by only putting an additional diode In series with the auxiliary switch. The operation of the auxiliary switch in a half wave mode makes it possible soft switching operation of all switches including the auxiliary switch whereas it is turned off with hard switching in conventional converter. The increase of the regeneration ratio to resonant energy results in low commutation losses and minimum voltage and current stresses. The operation principles of the improved ZVT PWM DC-DC Converters are theoretically analyzed using the boost converter topology as an example. Both theoretical analysis and experimental results verify the validity of the PWM boost converter topology with the improved full wave mode ZVT PWM converters.

• Journal of the Microelectronics and Packaging Society
• /
• v.13 no.4
• /
• pp.57-63
• /
• 2006

For chip-stack package applications, Cu filling characteristics into trench vias of $75{\sim}10\;{\mu}m$ width and 3 mm length were investigated with variations of electroplating current density and current mode. At $1.25mA/cm^{2}$ of DC mode, Cu filling ratio higher than 95% was obtained for trench vias of $75{\sim}35{\mu}m$ width. When electroplated at DC $2.5mA/cm^{2}$, Cu filling ratios became inferior to those processed at DC $1.25mA/cm^{2}$. Pulse current mode exhibited Cu filling characteristics superior to DC current mode.

• Journal of the Korean Society for Nondestructive Testing
• /
• v.20 no.1
• /
• pp.33-37
• /
• 2000

The 1-3 piezoelectric composite transducer with 75 volume percents PZT was fabricated by the dicing-filling method. The resonance modes of the 1-3 transducer have been studied with electric impedance measurement as a function of frequency. The fundamental frequencies of the planar and thickness mode were observed at 0.95MHz and 1.63MHz respectively, but the lateral mode was not observed. In the thickness mode, the electromechanical coupling coefficient of the 1-3 piezoelectric composite transducer, 0.54, was very closed to that of the single phase PZT(0.52). The pulse-echo response by exciting the 1-3 transducer with an electric pulse was observed from the water/reflector interface, and analyzed bandwidth by the spectrum of the impulse response. The quality factor Q for the 1-3 transducer was observed as 1.5 smaller than that of the single phase(80) and then the 1-3 transducer may be used to the broad band type transducer applications.