• 전력전자학회논문지
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• 제21권2호
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• pp.126-133
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• 2016

This paper proposes a new PWM method to reduce the common mode voltage change in three-level Vienna rectifier. This new proposed PWM method uses medium voltage vector for the three-level Vienna rectifier to determine the sum of three-phase voltage zero, and the common mode voltage variation is decreased. Using the carrier comparison method, the switching function generator for three-level Vienna rectifier has been proposed. The effects of the proposed PWM method have been verified through simulation using the PSIM.

• Journal of Power Electronics
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• 제16권1호
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• pp.142-152
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• 2016

Common mode voltage (CMV) generation is a major problem in switching power converter fed induction motor drive systems. CMV is the zero sequence voltage generated due to the switching action of power converters. Even a small magnitude of CMV with a high rate of change may circulate large bearing currents which may damage a machine's bearings and shorten its life. There are several methods of controlling CMV. This paper presents 3-level sinusoidal pulse width modulation based techniques to control the magnitude and rate of change of CMV in multilevel AC-DC-AC drive systems. Simulation and experimental investigations have been presented to validate the performance of proposed technique to control CMV in 3-level neutral point clamped inverter based AC-DC-AC system.

• Journal of Power Electronics
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• 제12권5호
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• pp.715-722
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• 2012

New discrete time domain models for the peak current controlled (PCC) power LED drivers in continuous conduction mode include for the first time the effects of the time delay in the pulse-width-modulator. Realistic amounts of time delay are found to have significant effects on the average output LED current and on the critical inductor value at the boundary between the two conduction modes. Especially, the time delay can provide an accurate LED current for the PCC buck converter with a wide input voltage. The models can also predict the critical inductor value at the mode boundary as functions of the input voltage and the time delay. The overshoot of the peak inductor current due to the time delay results in the increase of the average output current and the reduction of the critical inductor value at the mode boundary in all converters. Experimental results are presented for the PCC buck LED driver with constant-frequency controller.

• 전력전자학회논문지
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• 제27권5호
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• pp.446-454
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• 2022

This study proposes a carrier-based pulse width modulation (PWM) method for leakage current reduction and neutral point (NP) current control in a three-phase three-level converter, which is a carrier-based PWM version of the previously proposed low-frequency common mode voltage PWM. Three groups of space vectors with the same common mode voltage are used. When the averaged NP current needs to be positive or negative, the specific groups are employed to produce low-frequency common mode voltages. The validity of the proposed PWM method is verified through experiments.

• ETRI Journal
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• 제39권4호
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• pp.582-591
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• 2017

To address the wire complexity problem in large-scale globally asynchronous, locally synchronous systems, a current-mode ternary encoding scheme was devised for a two-phase asynchronous protocol. However, for data transmission through a very long wire, few studies have been conducted on reducing the long propagation delay in current-mode circuits. Hence, this paper proposes a current steering logic (CSL) that is able to minimize the long delay for the devised current-mode ternary encoding scheme. The CSL creates pulse signals that charge or discharge the output signal in advance for a short period of time, and as a result, helps prevent a slack in the current signals. The encoder and decoder circuits employing the CSL are implemented using $0.25-{\mu}m$ CMOS technology. The results of an HSPICE simulation show that the normal and optimal mode operations of the CSL achieve a delay reduction of 11.8% and 28.1%, respectively, when compared to the original scheme for a 10-mm wire. They also reduce the power-delay product by 9.6% and 22.5%, respectively, at a data rate of 100 Mb/s for the same wire length.

• Journal of Power Electronics
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• 제14권2호
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• pp.315-323
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• 2014

An optimized space vector pulse width modulation (SVPWM) method with common mode voltage elimination and neutral point potential balancing is proposed for an open-end winding induction motor. The motor is fed from both of the ends with two neutral point clamped (NPC) three-level inverters. In order to eliminate the common mode voltage of the motor ends and balance the neutral point potential of the DC link, only zero common mode voltage vectors are used and a balancing control factor is gained from calculation in the strategy. In order to improve the harmonic characteristics of the output voltages and currents, the balancing control factor is regulated properly and the theoretical analysis is provided. Simulation and experimental results show that by adopting the proposed method, the common mode voltage can be completely eliminated, the neutral point potential can be accurately balanced and the harmonic performance for the output voltages and currents can be effectively improved.

• Journal of Power Electronics
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• 제10권1호
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• pp.27-33
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• 2010

This paper presents a bidirectional DC-DC converter suitable for low-voltage super capacitor-based electric energy storage systems. The DC-DC converter presented here consists of a full-bridge circuit and a current-fed push-pull circuit with a high frequency (HF) transformer-link. In order to reduce the device-conduction losses due to the large current of the super capacitor as well as unnecessary ringing, synchronous rectification is employed in the super capacitor-charging mode. A wide range of voltage regulation between the battery and the super capacitor can be realized by employing a Phase-Shifting (PS) Pulse Width Modulation (PWM) scheme in the full-bridge circuit for the super capacitor charging mode as well as the overlapping PWM scheme of the gate signals to the active power devices in the push-pull circuit for the super capacitor discharging mode. Essential performance of the bidirectional DC-DC converter is demonstrated with simulation and experiment results, and the practical effectiveness of the DC-DC converter is discussed.

• 전력전자학회논문지
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• 제9권1호
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• pp.10-16
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• 2004

본 논문에서는 공진 에너지 회생율을 최대화하여 전체적인 효율을 증가시킨 개선된 전파형 ZVT(Zero-Voltage-Transition) PWM(Pulse-Width-Modulation) DC-DC 컨버터를 소개한다. 개선된 회로는 단지 기존 컨버터의 보조스위치와 공진형 인덕터 사이에 직렬로 역공진 저지 다이오드를 추가로 달아서 모든 스위칭 소자들이 소프트 스위칭 조건에서 턴온/턴오프하여 스위칭 손실을 최소화하고, 공진 에너지를 완전히 입력으로 회귀시켜 전도손실을 절감하여 효율의 증감을 이루었다. 본 논문에서는 부스터 컨버터를 이용하여 개선된 컨버터의 동작을 분석하고, 실험결과를 바탕으로 제안된 회로의 타당성을 입증하였다.

• 마이크로전자및패키징학회지
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• 제13권4호
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• pp.57-63
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• 2006

칩 스택 패키지의 삼차원 interconnection에 적용을 위해 폭 $75{\sim}10\;{\mu}m$, 길이 3mm의 트랜치 비아에 대해 전기도금전류밀도 및 전류모드에 따른 Cu filling 특성을 분석하였다. 직류모드로 $1.25mA/cm^{2}$에서 Cu filling한 경우, 트랜치 비아의 폭이 $75{\sim}35{\mu}m$ 범위에서는 95% 이상의 높은 Cu filling ratio를 나타내었다. 직류 전류밀도 $2.5mA/cm^{2}$에서 Cu filling한 경우에는 $1.25mA/cm^{2}$ 조건에 비해 열등한 Cu filling ratio를 나타내었으며, 직류모드에 비해 펄스모드가 우수한 Cu filling 특성을 나타내었다.

• 비파괴검사학회지
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• 제20권1호
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• pp.33-37
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• 2000

압전 세라믹 PZT와 고분자 매질인 에폭시 수지를 사용하여 PZT 체적비가 75%인 1-3 압전복합변환자를 dicing-filling 방법으로 제작하여 임피던스 분석과 펄스 반사법으로 수신된 초음파신호의 스펙트럼 분석을 통하여 전기 및 음향 특성을 조사하였다. 제작된 1-3 압전복합변환자의 경진동 모드 및 두께진동 모드의 기본진동수는 각각 0.95MHz와 1.63MHz이었고, 측면진동 모드는 관찰되지 않았다. 두께진동 모드에 대한 전기기계 결합계수는 PZT 단일상(0.52)보다 큰 0.54로 수신효율이 향상되었음을 알 수 있었다. 그리고 기계적 품질계수(Q)는 PZT 단일상(80)보다 상당히 작은 1.5이었고, 1-3 압전복합변환자의 축상 분해능이 크게 향상되었음을 알 수 있었다.