• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 추계학술대회 논문집 학회본부
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• pp.612-614
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• 1997

Silicon based micro mirror array is a highly efficient component for use in optical applications such as adaptive optical systems and optical correlators. A micro mirror array designed, fabricated and tested here is consisted of $5{\times}5$ single layer polysilicon, electrostatically driven actuators. In this paper, deflection characteristics and pull-in behavior of the actuators for analog control was studied and particularly, the influence of the residual stress in flexure beams for the restorative force of actuators was considered. The springs are modeled as a residual stress-free spring and a spring with residual stress. In calculation, a mirror with the residual stress-free springs has 30.3N/m spring constant and 31.1V pull-in voltage. On the other hand, a mirror with the stressed springs has 23.6N/m and 27.4V respectively. The experimental result, which is 20.5N/m and 25.5V, shows that the stressed springs ore well modeled.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권4호
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• pp.288-294
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• 2002

This paper presents the design, fabrication and characterization of a 32 by 32 electroplated micromirror array on a glass, a low cost substrate. Approaches taken in this work for the fabrication of micromachined mirror arrays include a line addressing scheme, a seamless array design for high fill factor, planarization techniques of polymeric interlayers, a high yield methodology for the removal of sacrificial polymeric interlayers, and low temperature and chemically safe fabrication techniques. The micromirror is fabricated by aluminum and the size of a single micromirror is 200 $\mu\textrm{m}{\;}{\times}200{\;}\mu\textrm{m}$. Static deflection test of the micro-mirror has been carried out and pull-in voltage of 44V and releasing voltage of 30V was found.

• 전력전자학회논문지
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• 제9권6호
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• pp.577-583
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• 2004

액정 디스플레이의 백라이트에 사용되는 냉음극 방전램프(CCFL: Cold Cathode Fluorescent Lamp) 구동을 위해 압전 변압기(Piezoelectric Transformer)를 사용하였으며, 최적 파라미터를 선정하여 실험을 통해 검증하였다. 적용한 압전 인버터로는 푸시-풀(Push-Pull)회로와 하프-브리지(Half-Bridge) 회로이며, 휘도 제어기법으로는 각각 아날로그(Analog) 방식과 버스트(Burst) 방식을 사용하였다. 푸시-풀 인버터의 경우 아날로그 제어방식으로 제어전압 2.5-4.5V에서 출력전류 1-6mA로 휘도 0-100% 특성을 보였다. 입출력 효율로 90.3%를 얻었으며, 하프브리지 인버터에 적용한 버스트 제어방식에서는 듀티비 5-50%에서 1-6mA의 제어 성능을 보였으며, 인버터의 입출력 효율은 82.1%를 얻었다.

• 한국정보통신학회논문지
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• 제13권9호
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• pp.1858-1864
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• 2009

본 논문에서는 power management IC에 사용되는 비휘발성 메모리 IP인 1-kd OTP IP를 설계하였다. 기존의 OTP 셀 (cell)은 isolated NMOS 트랜지스터를 안티퓨즈 (antifuse)로 사용하였으나 BCD 공정에서는 셀 크기가 큰 단점이 있다. 그래서 본 논문에서는 isolated NMOS 트랜지스터 대신 PMOS 트랜지스터를 안티퓨즈로 사용하였으며, OTP 셀 트랜지스터의 크기를 최적화시켜 셀의 크기를 최소화시켰다. 그리고 ESD 테스터 시 PMOS 안티퓨즈 양단에 고전압 (high voltage)가 걸려 임의의 셀이 프로그램 되는 것을 방지하기 위하여 OTP 코어 회로에 ESD 보호 회로 (protection circuit)를 추가하였다. 또한 프로그램 되지 않은 셀을 읽을 때 게이트 커플링 노이즈를 제거하기 위해 high-impedance의 PMOS pull-up 트랜지스터를 ON 시키는 방식을 제안하였다. 동부하이텍 $0.18{\mu}m$ BCD 공정을 이용하여 설계된 1-kb PMOS-type 안티퓨즈 OTP IP의 레이아웃 크기는 $129.93{\times}452.26{\mu}m^2$이다.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2012년도 춘계학술대회
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• pp.722-725
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• 2012

본 논문에서는 프로그램 된 eFuse 링크의 센싱 저항이 작으면서 기준 전압없이 BL 데이터를 센싱가능한 differential paired eFuse 셀을 사용하여 BCD 공정 기반의 8비트 eFuse OTP를 설계하였다. Differential eFuse OTP 셀의 프로그램 트랜지스터의 채널 폭은 $45{\mu}m$과 $120{\mu}m$으로 split하였다. 그리고 프로그램된 eFuse 저항의 변동을 고려한 variable pull-up load를 갖는 센싱 마진 테스터(sensing margin test) 회로를 구현하였다. $0.35{\mu}m$ BCD 공정을 이용하여 제작된 8bit eFuse OTP IP를 측정한 결과 프로그램 트랜지스터의 채널 폭이 $120{\mu}m$인 OTP IP의 수율이 $45{\mu}m$인 OTP IP보다 양호한 것으로 나타났다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.227-231
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• 2003

In This paper, A novel zero-voltage-switching(ZVS) resonant DC-DC converter is proposed. it is composed of two symmetrical active-clamped circuits, The converter can achieve each switchs ZVS. proposed circuit is active clamp capacitor Ratios can be reduce switching voltage stress of each main switch. Simulation results using Pspice ver 9.2 show that the prove the validity of theoretical analysis.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 B
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• pp.837-839
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• 2001

This paper presents dynamic characteristic of a 2 phase hybrid stepping motor which includes pull-out torque with constant voltage drive and one step response. In order to analyze this characteristics, vector diagram of a synchronous motor and torque-voltage equation are used. Analytic results are good agreement with experimental results.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1117-1120
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• 2003

In this paper, a 1.5V CMOS high frequency operational amplifier for high frequency signal processing systems is presented. For obtaining the high gain and the high unity gain frequency with the 1.5V supply voltage, the op-amp is designed with simple two stages which are consisting of the rail-to-rail differential input stage and the class-AB output stage. The designed op-amp operates with the 1.5V supply voltage, and shows well the push-pull class-AB operation. The simulation results show the DC open loop gain of 77dB and the unity gain frequency of 100MHz for the 1㏁ ┃ 10pF load. When the resistive load R$_1$. is varied from 1㏁ to 1 ㏀, the DC open loop gain decreases by only 4dB.

• 전자공학회논문지C
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• 제34C권10호
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• pp.19-26
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• 1997

Novel class AB CMOS second-generation current conveyors (CCII) using 0.6.mu.m n-well CMOS process for high-frequency current-mode signal processing were developed. The CCII for low power operation consists of a class AB push-pull stage for the current input, a complementary source follower for the voltage input, and a cascode current mirror for the current output. In this architecture, the two input stages are coupled by current mirrors to reduce the current input impedance. Measurements of the fabricated CCII show that the current input impedance is 875.ohm. and the bandwidth of flat gain when used as a voltage amplifier extends beyond 4MHz. The power dissipation is 1.25mW and the active chip area is 0.2*0.15[mm$\^$2/].

• 한국전기전자재료학회논문지
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• 제15권9호
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• pp.743-749
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• 2002

A 1.5V 70㏈ 100MHz CMOS class-AB complementary operational amplifier is presented. For obtaining the high gain and the high unity gain frequency, the input stage of the amplifier is designed with rail-to-rail complementary differential pairs which are symmetrically parallel-connected with the NMOS and the PMOS differential input pairs, and the output stage is designed to the rail-to-rail class-AB output stage including the elementary shunt stage technique. With this design technique for output stage, the load dependence of the overall open loop gain is improved and the push-pull class-AB current control can be implemented in a simple way. The designed operational amplifier operates perfectly on the complementary mode with 180$^{\circ}$ phase conversion for 1.5V supply voltage, and shows the push-pull class-AB operation. In addition, the amplifier shows the DC open loop gain of 70.4 ㏈ and the unity gain frequency of 102 MHz for $C_{L=10㎊∥}$ $R_{L=1㏁}$ Parallel loads. When the resistive load $R_{L}$ is varied from 1 ㏁ to 1 ㏀, the DC open loop gain of the amplifier decreases by only 2.2 ㏈.a$, the DC open loop gain of the amplifier decreases by only 2.2 dB.