• 제목/요약/키워드: Pull down test

검색결과 25건 처리시간 0.027초

게이트 레벨 천이고장을 이용한 BiCMOS 회로의 Stuck-Open 고장 검출 (Detection of Stuck-Open Faults in BiCMOS Circuits using Gate Level Transition Faults)

  • 신재흥;임인칠
    • 전자공학회논문지A
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    • 제32A권12호
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    • pp.198-208
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    • 1995
  • BiCMOS circuit consist of CMOS part which constructs logic function, and bipolar part which drives output load. Test to detect stuck-open faults in BiCMOS circuit is important, since these faults do sequential behavior and are represented as transition faults. In this paper, proposes a method for efficiently detecting transistor stuck-open faults in BiCMOS circuit by transforming them into slow-to=rise transition and slow-to-fall transition. In proposed method, BiCMOS circuit is transformed into equivalent gate-level circuit by dividing it into pull-up part which make output 1, and pull-down part which make output 0. Stuck-open faults in transistor are modelled as transition fault in input line of gate level circuit which is transformed from given circuit. Faults are detceted by using pull-up part gate level circuit when expected value is '01', or using pull-down part gate level circuit when expected value is '10'. By this method, transistor stuck-open faults in BiCMOS circuit are easily detected using conventional gate level test generation algorithm for transition fault.

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Analysis of instrument exercise using IMU about symmetry

  • Yohan Song;Hyun-Bin Zi;Jihyeon Kim;Hyangshin Ryu;Jaehyo Kim
    • International Journal of Advanced Culture Technology
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    • 제11권1호
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    • pp.296-305
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    • 2023
  • The purpose of this study is to measure and compare the balance of motion between the left and right using a wearable sensor during upper limb exercise using an exercise equipment. Eight participants were asked to perform upper limb exercise using exercise equipment, and exercise data were measured through IMU sensors attached to both wrists. As a result of the PCA test, Euler Yaw(Left: 0.65, Right: 0.75), Roll(Left: 0.72, Right: 0.58), and Gyro X(Left: 0.64, Right: 0.63) were identified as the main components in the Butterfly exercise, and Euler Pitch(Left: 0.70, Right 0.70) and Gyro Z(Left: 0.70, Right: 0.71) were identified as the main components in the Lat pull down exercise. As a result of the Paired-T test of the Euler value, Yaw's Peak to Peak at Butterfly exercise and Roll's Mean, Yaw's Mean and Period at Lat pull down exercise were smaller than the significance level of 0.05, proving meaningful difference was found. In the Symmetry Index and Symmetry Ratio analysis, 89% of the subjects showed a tendency of dominant limb maintaining relatively higher angular movement performance then non-dominant limb as the Butterfly exercise proceeds. 62.5% of the subjects showed the same tendency during the Lat pull down exercise. These experimental results indicate that meaningful difference at balance of motion was found according to an increase in number of exercise trials.

Domino CMOS NOR-NOR Array Logic의 Testable Design에 관한 연구 (A Study on Testable Design and Development of Domino CMOS NOR-NOR Array Logic)

  • 이중호;조상복;정천석
    • 대한전자공학회논문지
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    • 제26권6호
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    • pp.131-139
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    • 1989
  • 본 논문에서는 CMOS 및 domino CMOS 의 특징과 PLA등 array logic의 특징을 동시에 살리면서 동작특성이 좋고 집적도가 높으며 테스트 생성이 쉬운 domino CMOS NOR-NOR array logic의 설계방식을 제안하였다. 이 방식은 pull-down 특성을 개선하여 기생 커패시턴트의 문제점을 해결하며 간단한 부가회로를 사용하여 회로내의 모든 고정들을 검출할 수 있도록 한 testable design 방식이다. PLA의 적항군의 개념 및 특성 행렬을 이용한 테스트 생성 알고리듬과 절차를 제안하였고 이를 PASCAL 언어로 실현하였다. 또한 SPICE 및 P-SPICE를 이용하여 본 설계방식에 대한 검증을 행하였다.

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BiCMOS 회로의 Stuck-Open 고장 검출을 위한테스트 패턴 생성 (Test Pattern Generation for Detection of Sutck-Open Faults in BiCMOS Circuits)

  • 신재홍
    • 전기학회논문지P
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    • 제53권1호
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    • pp.22-27
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    • 2004
  • BiCMOS circuit consist of CMOS part which constructs logic function, and bipolar part which drives output load. In BiCMOS circuits, transistor stuck-open faults exhibit delay faults in addition to sequential behavior. In this paper, proposes a method for efficiently generating test pattern which detect stuck-open in BiCMOS circuits. In proposed method, BiCMOS circuit is divided into pull-up part and pull-down part, using structural property of BiCMOS circuit, and we generate test pattern using set theory for efficiently detecting faults which occured each divided blocks.

BiCMOS 회로의 고장 검출을 위한 테스트 패턴 생성 (Test Pattern Generation for Detection of faults in BiCMOS Circuits)

  • 신재흥;이병효;김일남;이복용
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2003년도 학술대회 논문집 전문대학교육위원
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    • pp.113-116
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    • 2003
  • BiCMOS circuit consist of CMOS part which constructs logic function, and bipolar part which drives output load. In this paper, proposes a method for efficiently generating test pattern which detect faults in BiCMOS circuits. In proposed method, BiCMOS circuit is divided into pull-up part and pull-down part, using structural property of BiCMOS circuit, and we generate test pattern using set theory for efficiently detecting faults which occured each divided blocks.

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BiCMOS 회로의Stuck-Open 고장과 Stuck-On 고장 검출을 위한 테스트 패턴 생성 (Test Pattern Genration for Detection of Stuck-Open and Stuck-On Faults in BiCMOS Circuits)

  • 신재흥;임인칠
    • 전자공학회논문지C
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    • 제34C권1호
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    • pp.1-11
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    • 1997
  • A BiCMOS circuit consists of the CMOS part which performs the logic function, and the bipolar part which drives output load. In BiCMOS circuits, transistor stuck-open faults exhibit delay faults in addition to sequential beavior. Also, stuck-on faults enhanced IDDQ (quiscent power supply current) at steady state. In this paper, a method is proposed which efficiently generates test patterns to detect stuck-open faults and stuck-on faults in BiCMOS circuits. The proposed method divides the BiCMOS circuit into pull-up part and pull-down part, and generates test patterns detect faults occured in each part by structural property of the BiCMOS circuit.

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전류 경로 그래프를 이용한 BiCMOS회로의 단락고장 검출 (On the detection of short faults in BiCMOS circuits using current path graph)

  • 신재흥;임인칠
    • 전자공학회논문지A
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    • 제33A권2호
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    • pp.184-195
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    • 1996
  • Beause BiCMOS logic circuits consist of CMOS part which constructs logic function and bipolar part which drives output load, the effect of short faults on BiCMOS logic circuits represented different types from that on CMOS. This paper proposes new test method which detects short faults on BiCMOS logic circuits using current path graph. Proposed method transforms BiCMOS circuits into raph constructed by nodes and edges using extended switch-level model and separates the transformed graph into pull-up part and pull-down part. Also, proposed method eliminates edge or add new edge, according ot short faults on terminals of transistor, and can detect short faults using current path graph that generated from on- or off-relations of transistor by input patterns. Properness of proposed method is verified by comparing it with results of spice simulation.

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경영정보학의 학문적 위상에 관한 연구 (A Study on the Scientific Status of MIS)

  • 오재인
    • Asia pacific journal of information systems
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    • 제8권3호
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    • pp.181-194
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    • 1998
  • The inability of the management information systems (MIS) field to progress as a scientific discipline has been attributed to the lack of systematic research and a cumulative tradition, an identity crisis, and the poverty of scientism. While research on the status of MIS is very important in order to enhance the field as a scientific discipline, few have investigated this issue. Following Thomas Kuhn's idea of paradigm, this paper studies other fields to investigate when they progressed, when they did not, and why. After research paradigm was broken down into technology-push and demand-pull types, a model on the science life cycle was developed in an effort to explain the path how a science has progressed. A test of this model in the fields of physics and chemistry with an old historial background reveals that the scientific progress in the area of demand-pull is more desirable if this progress turns out to be in the right direction. An application of the model to the MIS field shows that the research paradigm in this field is mainly of technology-push. In order to shift this paradigm toward the demand-pull area, this paper suggests the research on the relationship among MIS subfields and the adoption of appropriate reference disciplines.

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기피-유인을 이용한 바퀴의 효율적 방제 (Effective Control in Managing German Cockroach, Blattella germanica (Orthoptera: Blatellidae) Using a Push-Pull Strategy)

  • 양정오;김상우;노두진;윤창만;강신호;김길하
    • 농약과학회지
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    • 제12권2호
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    • pp.162-167
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    • 2008
  • 제한된 주거공간에서 바퀴의 방제효과를 높이기 위하여 한쪽에 기피성분(push)을 처리하고 반대쪽에 일반적인 유인성분(pull)이 포함된 독먹이제(bait)를 처리함으로서 행동자극에 의한 기피-유인 방제효과를 검증하였다. 먼저 상형장치를 이용한 mini-field 시험에서, 바퀴는 기피제형이 처리된 장소로부터 벗어나서 유인 먹이가 처리된 곳으로 몰려들었으며, 처리된 유인먹이와 독먹이의 소비량은 기피-유인 효과에 의해 밀집된 곳의 먹이에서 높게 나타났다. 따라서 바퀴에 대하여 기피 효과가 우수한 식물정유를 선별 적용함으로서 살충효과를 높이기 위하여 Citrus 속의 grapefruit, lemon, lime, orange, 그리고 petitgrain 오일에 대한 기피-유인 살충효과를 평가하였다. 동시 처리된 기피-유인 처리는 유인 독먹이만 처리된 대조구에 비해 더 빠르고 높은 살충효과를 나타냈으며, Citrus 속 오일의 기피에 의한 살충효과는 grapefruit > lemon > lime > orange > petitgrain 오일 순으로 나타났다. 따라서 본 실험은 제한된 공간에서 기피제로서 Citrus속 오일과 기피-유인 방법을 이용하는 효율적인 방제법을 제시한다.

GF/PP 복합재료의 충격파괴거동에 대한 온도효과 (Temperature Effect on Impact Fracture Behavior of GF/PP Composites)

  • 고성위;엄윤성
    • 수산해양기술연구
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    • 제41권1호
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    • pp.78-84
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    • 2005
  • The main goal of this work is to study the effects of temperature and volume fraction of fiber on the Charpy impact test with GF/PP composites. The critical fracture energy and failure mechanisms of GF/PP composites are investigated in the temperature range of 60^{\circ}C$ to -50^{\circ}C$ by impact test. The critical fracture energy increased as the fiber volume fraction ratio increased. The critical fracture energy shows a maximum at ambient temperature and it tends to decreases as temperature goes up or goes down. Major failure mechanisms can be classified such as fiber matrix debonding, fiber pull-out and/or delamination and matrix deformation.