• Title/Summary/Keyword: Protocol Design and Verification

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Algorithm Design and Implementation of Interworking with MR for NEMO in PMIPv6 Network (PMIPv6 망에서 NEMO 지원을 위한 MR 연동 알고리즘의 설계 및 구현)

  • Min, Sang-Won
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.34 no.6B
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    • pp.615-622
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    • 2009
  • In this paper, we consider the problem of applying NEMO in PMIPv6, and propose a method to support network mobility. When an MR enters a PMIPv6 domain, an MAG recognizes the MR to access using the BU message. And the MAG makes a tunnel between the MAG and the MR. The MR do not make tunnel fundamentally except for handover. Therefore, the PMIPv6 protocol needs to modify the original algorithm and the BCE data filed. However, the proposed method can use NEMO without protocol modification. To show verification, we implement our proposed algorithm with added BCE data filed using C program, and configure a testbed network. Through a network connectivity procedure, we can see that our proposed method can support network mobility within the PMIPv6 network.

Global Healthcare Information System

  • Singh, Dhananjay;Lee, Hoon-Jae;Chung, Wan-Young
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2008.10a
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    • pp.365-368
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    • 2008
  • This paper presents a new concept of IP-based wireless sensor networks and also introduces a routing protocol that is based on clustering for global healthcare information system. Low-power wireless personal area networks (LoWPANs) conform the standard by IEEE 802.15.4-2003 to IPv6 that makes 6lowpan. It characterized by low bit rate, low power, and low cost as well as protocol for wireless connections. The 6lowpan node with biomedical sensor devices fixed on the patient body area network that should be connected to the gateway in personal area network. Each 6lowpan nodes have IP-addresses that would be directly connected to the internet. With the help of IP-address service provider can recognize or analysis patient biomedical data from anywhere on globe by internet service provider equipments such as cell phone, PDA, note book. The system has been evaluated by technical verification, clinical test, user survey and current status of patient. We used NS-2.33 simulator for our prototype and also simulate the routing protocols. The result shows the performance of biomedical data packets in multi-hope routing as well as represents the topology of the networks.

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An Efficient Stream Authentication Scheme using Tree Authentication (인증 트리 기법을 이용한 효율적인 스트림 인증 기법)

  • Park, Yong-Su;Cho, Yoo-Kun
    • Journal of KIISE:Computer Systems and Theory
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    • v.29 no.8
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    • pp.484-492
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    • 2002
  • We propose an efficient stream authentication scheme using tree authentication. To reduce the computation cost of the sender, we design the authentication tree whose height is very short. We appropriately distribute authentication information over packets so the receiver can verify data with high probability. Moreover, we provide mathematical analysis on the verification probability. For the proposed scheme and previous schemes, we measured the elapsed time for generating authentication information and the proposed scheme has equal to or slightly larger than that of GM's scheme, which has the lowest computation overhead. We performed simulations, which show that the verification probability of the proposed scheme is much higher than that of any other scheme.

A Transactor Implementation for SoC Verification with iPROVE (iPROVE 기반 SoC 검증을 위한 트랜잭터 구현)

  • Cho, Chong-Hyun;Cho, Joong-Hwee
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.4
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    • pp.73-79
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    • 2007
  • In this paper the proposed transactor is customized and a generator which roles of automatically generating the transactor according to DUT(Design Under Test)'s input and output is implemented. The customized transactor is designed by rearranging the signals of depending on DUT and transactor protocol which consists of signals of the PCI interface between host computer and FPGA(Field Programmable Gate Array). The implemented automatic generator of transactor generates a Verilog code of transactor by adding DUT's information about input and output ports. Performance and normal working of the generated transactor has been verified by experiments with some verified hardware IPs. Also, an efficiency of the transactor has been verified by comparing with user's manually designed transactor and generated transactor. Moreover, the generator's flexibility has been verified for DUT's information of variable input and output. In case of using the implemented generator, a design time of transactor is reduced.

Development of Auto-tuning Temperature Controller with Multi-channel (다중채널을 갖는 오토튜닝 온도 제어기 개발)

  • Lee, Kap Rai
    • The Journal of the Convergence on Culture Technology
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    • v.4 no.4
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    • pp.419-427
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    • 2018
  • This paper designs and develops auto-tuning temperature controller with multi-channel, which controller with multi-channel could control a number of control system simultaneously. This controller has multi-channel input and output. And a number of control algorithms run in this controller simultaneously and independently. Firstly we present design method of controller with multi-channel. Secondly we design electrical circuit of sensor input, controller output and power control for temperature control board. And finally we design data protocol for serial communication to monitor control state and present verification of temperature controller with muiti-channel through field experiment.

Implementation of RFID Baseband system for Sensor Network (센서네트워크용 RFID Baseband 시스템 구현)

  • Lee, Doo Sung;Kim, Sun Hyung
    • Journal of Korea Society of Digital Industry and Information Management
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    • v.4 no.4
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    • pp.9-19
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    • 2008
  • In this paper, it is studied anti-collision algorithm based on the transmission protocol for RFID baseband system of the lSO/IEC 18000-6 Type-C regulation and designed the baseband part of RFID reader system using FPGA. To compensate this weak point of the slot random aloha algorithm which must have a long time to be dumped before deciding an appropriate slot size according to the number of surrounding tag, we suggested how to apply Bit By Bit algorithm to be able to recognize the tag when the tag is clashing. The design of the baseband part in the RFID reader system is accomplish by use of the ISE9.1i and I made an experiment on it targeting Spartan2. Construction verification is measured each block through Logic Analyzer and I can verify it has no error. I also compared and analyzed the performance between proposed algorithm and past algorithm and verified the improvement of performance.

Implementation of Analysis Tool and Design of Event Recorder in Express Railway (고속열차용 Event Recorder 설계와 분석도구의 구현)

  • Kim, Kwang-Ryul;Jang, Dong-Wook;Han, Kwang-Rok;Sohn, Surg-Won;Ryu, Hee-Mon;Song, Gyu-Youn
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.1159-1160
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    • 2008
  • For safety railway vehicle movement, analysis and recoding of railway vehicle speed and driving information has written by law. nowadays, base in europe, these system is spread of various advanced country. In this paper, We implement an event recorder which record the driving and breaking information of running railway vehicle. For the event recorder, We designed the data structures with data analysis tools and a protocol between Event recorder and data analysis tool. The verification of Analysis tool was tested by to made data by Event Recorder's emulator and information of real railway driving recording.

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Design and Verification of Automotive CAN Controller (차량용 CAN 제어기의 설계 및 검증)

  • Lee, Jong-Bae;Lee, Seongsoo
    • Journal of IKEEE
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    • v.21 no.2
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    • pp.162-165
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    • 2017
  • CAN (controller area network) is a standard real-time serial communication protocol, and it was developed to control various in-vehicle electronic modules. In this paper, a CAN controller was designed in Verilog HDL, based on CAN ver. 2.0A and 2.0B. The designed CAN controller was implemented in FPGA, and it was verified its operation by connecting commercial chips. Its size is about 7,800 gates when synthesized in 0.18um technology.

Design and Verification of Automotive LIN Controller (차량용 LIN 제어기의 설계 및 검증)

  • Lee, Jong-Bae;Lee, Seongsoo
    • Journal of IKEEE
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    • v.20 no.3
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    • pp.333-336
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    • 2016
  • LIN (local interconnect network) is a standard low-speed serial communication protocol, and it was developed as an efficient sub-bus for automotive electronic modules. In this paper, a LIN controller was implemented in Verilog HDL, based on LIN ver. 2.2A. The implemented LIN controller was verified in FPGA, and it can be supplied as an IP to be integrated into SoC system. Its size is about 2,300 gates when synthesized in 0.18um technology.

Implementation of Embedded Educational Router System (임베디드 교육용 라우터 실습장비의 구현)

  • Park, Gyun Deuk;Chung, Joong Soo;Jung, Kwang Wook
    • Journal of the Korea Society of Computer and Information
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    • v.18 no.5
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    • pp.9-17
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    • 2013
  • This paper presents the design of the educational router system. This system is designed and implemented to support network configuration and embedded programming technology of the user on Internet. Not only Static routing protocol but also a kind of dynamic routing protocols such as OSPF and RIP and firewall have been programmed for education based on ethernet interface. ADS 1.2 as debugging environment, uC/OS-ii as RTOS and C language as development language are used. The educational procedures is compile, loading of static routing protocol, a kind of dynamic routing protocols such as OSPF and RIP and firewall program already supplied. Thereafter the verification is checked by using "ping" test to allow for demo operation such as hands-on training procedure. Finally programming procedure similar with demo operation of static routing protocol, a kind of dynamic routing protocols such as OSPF and RIP and packet filtering function is educated step by step.