• Applied Science and Convergence Technology
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• v.23 no.1
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• pp.34-39
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• 2014

The programmable switches which control the delivery of electrical signals in programmable logic devices are fabricated using memory technology. Although phase change memory (PCM) technology is one of the most promising candidates for the manufacturing of the programmable switches, the threshold switching material should be added to a PCM cell for realization of the programmable switches based on PCM technology. In this work, we report the impurity-doped $Ge_2Sb_2Te_5$ (GST) chalcogenide alloy exhibiting threshold switching property. Unlike the GST thin film, the doped GST thin film prepared by the incorporation of In and P into GST is not crystallized even at the postannealing temperature higher than $200^{\circ}C$. This specific crystallization behavior in the doped GST thin film is attributed to the stabilization of the amorphous phase of GST by In and P doping.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.4
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• pp.142-151
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• 1996

This paper presents a new symmetrical routing architecture for FPGA and an efficient routing algorithm for the architecture. The routing architecture adopts the segmented wires and the improved switch modules. Segmetned wires construct routing channels which pass through the chip in vertical and horizontal directions. To maximize the utility of a track, a track in each switch module can be separated in two part using a programmable switch to route two different net. The proposed routing algorithm finds all assignable tracks for a given net and selects the best track from assignable tracks to minimize the number of programmable switches and the unused portion of the wire segments. In order to stabilize the perfomrance of the algorithm, the routing order is defined by weighted sum of the number of wire segment, the length of wire segmetn, and the number of pin. Experimental results show that routability is improved dramatically and the number of crossing switches are reduced about 40% compared with the previous works.

• Journal of Internet of Things and Convergence
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• v.6 no.1
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• pp.97-102
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• 2020

Multi-Channel Switch ICs for IoT have integrated several solid state structure low ON-resistance bi-directional relay MOS switches with level shifter to drive high voltage and they should be independently controlled by external serialized logic control. These devices are designed for using in applications requiring high-voltage switching control by low-voltage control signals, such as medical ultra-sound imaging, ink-jet printer control, bare board open/short and leakage test system using Kelvin 4-terminal measurement method. This paper describes implementation of analog switch control block and its verification using Field programmable Gate Array (FPGA) test pattern generation. Each block has been implemented using Verilog hardware description language then simulated by Modelsim and prototyped in a FPGA board. Compare to conventional IC, The proposed architecture can be applied to fields where multiple entities need to be controlled simultaneously in the IoT environment and the proposed pattern generation method can be applied to test similar types of ICs.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.32 no.7
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• pp.254-260
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• 1983

In this paper a basic design procedure for programmable instruments of IEEE-488 BUS system has been discussed by designing a specific programmable frequency counter with its hardware and software. The designed programmable frequency counter has a programmable range switch and a function of the programable number of measurements. It contains five basic functions(Talker. Listener, Source handshake, Accepter handshake and Controller) of a IEEE-488 BUS and the Device-Trigger as a supplimentary function. The hardware has been built along with 6800 MPU and 68488 GPIA, and its software has included initialization, interrupt handler, BI.GET,BO and controller routines, The designed system given in this paper has been successfuly tested via some experiments.

• Proceedings of the KSR Conference
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• 2002.10b
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• pp.995-1000
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• 2002

This paper presents general concept of DC switch gear(DCSWGR). Normally, DCSWGR consist of Digital protection unit(DPU), High Speed Circuit Breaker(HSCB), Disconnect Switch (DS), Programmable Logic Control(PLC), Auxiliary Relays and etc. Most of the components has its special characteristics and their interface between each others are various and complex. In this paper every constituent general design are preceded and interface between each component are examined. And also DCSWGR operation logic with logical diagram including interlock signal are introduced.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.12
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• pp.953-958
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• 2001

The antifuse is a semi-permanent memory device like a ROM which shows the open or short state, and a switch device connecting logic blocks selectively in FPGA. In addition, the antifuse has been used as a logic device to troubleshoot defective memory cells arising from SDRAM processing. In this study, we have fabricated ONO antifuses consisted of PIP structure. The antifuse shows a high resistance more than several G Ω in the normal state, and shows a low resistance less than 500 Ω after program. The program resistance variation according to temperature shows the very stable value of $\pm$20 Ω. At this time, its program voltage shows 6.7∼7.2 V and the program is performed within 1 second. Therefore this result shows that the PIP antifuse is a very stable and programmable logic device.

• 한국ITS학회:학술대회논문집
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• 2008.11a
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• pp.347-350
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• 2008

• Journal of the Korean Vacuum Society
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• v.17 no.4
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• pp.253-261
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• 2008

Programmable metallizaton cell (PMC) memory device has been known as one of the next generation non-volatile memory devices, because it includes non-volatility, high speed and high ON/OFF resistance ratio. This paper reviews the operation principle of the device. Besides, the recent research results of professor Kozicki who firstly invented the device and investigated it for the memory applications, NEC corporation which studied it for the FPGA (field programmable gate array) switch applications, ETRI and chungnam national university which examined Te-based devices are introduced.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.8
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• pp.1580-1584
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• 2009

We have theoretically analyzed the monolithic integration of vertical cavity lasers with depleted optical thyristor (VCL-DOT) structure and experimentally demonstrated optical logic gates such as AND-gate, OR-gate, and INVERTER implemented by VCL-DOT for an optical programmable gate array. The optical AND and OR gates have been realized by changing a input bias of the single VCL-DOTs and all kinds of optical logic functions are also implemented by adjusting an intensity of the reference input beams into the differential VCL-DOTs. To achieve the high sensitivity, high slope efficiency and low threshold current, a small active region of lasing part and a wide detecting area are simultaneously designed by using a selective oxidation process. The fabricated devices clearly show nonlinear s-shaped current-voltage characteristics and lasing characteristics of a low threshold current with 0.65 mA and output spectrum at 854 nm.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.369-372
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• 2001

This paper presents the design of high-speed virtual output queue(VOQ) management scheme for high performance cell/packet switch, which has a serial cross bar structure. The proposed VOQ management scheme has been designed for wire-speed routing with a pipelined buffer management. It provides the tolerance of requests and grants data transmission latency between the VOQ manager and central arbiter using a new request control method that is based on a high-speed shifter. The designed VOQ manager has been implemented in a field programmable gate array chip with a 77MHz operating frequency, a 900-pin fine ball grid array package, and 16$\times$16 switch size.