• Proceedings of the IEEK Conference
• /
• 2002.07b
• /
• pp.778-781
• /
• 2002

In this paper, we designed the anti-fuse program circuit, and there are an anti-fuse program/sense/latch circuit, a negative voltage generator, power-up circuit and etc. in this circuit. An output voltage of a negative voltage generator is about -4,51V. We detected certainly it regardless of simulation result power rise time or temperature change to detect the anti-fuse program state of an anti-fuse program/sense/latch circuit and were able to know what performed a steady action. And as a result of having done a simulation while will change a resistance value voluntarily in order to check an anti-fuse resistance characteristic of this circuit oneself, it recognized as a programmed anti-fuse until 23k$\Omega$, and we were able to know that this circuit was a lot of margin than general anti-fuse resistance 500$\Omega$. Therefore, the anti-fuse program circuit of this study showed that was able to apply for configuration of the programmable logic device.

• ETRI Journal
• /
• v.42 no.4
• /
• pp.534-548
• /
• 2020

This study presents a new architecture for a field programmable analog array (FPAA) for use in low-frequency applications, and a generalized circuit realization method for the implementation of nth-order elliptic filters. The proposed designs of both the FPAA and elliptic filters are based on the operational transconductance amplifier (OTA) used in implementing OTA-C filters for biopotential signal processing. The proposed FPAA architecture has a flexible, expandable structure with direct connections between configurable analog blocks (CABs) that eliminates the use of switches. The generalized elliptic filter circuit realization provides a simplified, direct synthetic method for an OTA-C symmetric balanced structure for even/odd-nth-order low-pass filters (LPFs) and notch filters with minimum number of components, using grounded capacitors. The filters are mapped on the FPAA, and both architectures are validated with simulations in LTspice using 90-nm complementary metal-oxide semiconductor (CMOS) technology. Both proposed FPAA and filters generalized synthetic method achieve simple, flexible, low-power designs for implementation of biopotential signal processing systems.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.6 s.360
• /
• pp.34-41
• /
• 2007

We popose a programmed on-line to FSM-based Programmable BIST(Buit-In Self-Test) with selected command, to select a test algorithm from a predetermined set of algorithms that are built in the Flash memory BIST. Thus, the proposed scheme greatly simplifies the testing process. Besides, the proposed FSM-based Programmable BIST is more efficient in terms of circuit size and test data to be applied, and it requires less time to configure the Flash memory BIST. We also will develop a programmable Flash memory BIST generator that automatically produces Verilog code of the proposed BIST architecture for a given set of test algorithms. If experiment the proposed method, the proposed method will achieves a good flexibility with smaller circuit size compared with previous methods.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
• /
• 2003.10a
• /
• pp.127-130
• /
• 2003

An RSFQ (Rapid Single Flux Quantum) counter can be used as a frequency divider that was an essential part of a programmable voltage standard chip. The voltage standard chip is composed of two circuit parts, a counter and an antenna Analog signal of tens to hundreds ㎓ may be applied to a finline antenna part. This analog signal can be converted to the stream of SFQ voltage pulses by a DC/SFQ circuit. The number of voltage pulses can be reduced by 2n times when they pass through a counter that is composed of n T Flip-Flops (Toggle Flip-Flop). Such a counter can be used not only as a frequency divider, but also to build a programmable voltage standard chip. So, its application range can be telecommunication, high speed RAM, microprocessor, etc. In this work, we have used Xic, WRspice, and L-meter to design an RSFQ counter. After circuit optimization, we could obtain the bias current margins of the T Flip-Flop circuit to be above 31％ Our RSFQ counter circuit designs were based on the 1 ㎄/$\textrm{cm}^2$ niobium trilayer technology.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.18 no.10
• /
• pp.1527-1536
• /
• 1993

A new transmitter circuit for remote controllers is designed to provide flexibility and expandibility in function. The circuit employs a microcode approach to accept various code format, length and pulse widths through programming, and the precessing logics is eliminated to reduce its size. The circuit was Implemented using FPGA(Field Programmable Gate Array) and it was found to operate successfully).

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.10
• /
• pp.59-66
• /
• 1997

Neural networks has widely been be used for several practical applications such as speech, image processing, and pattern recognition. Thus, a approach to the voltage-controlled current source in areas of neural networks, the key features of CNN in locally connected only to its netighbors. Because the architecture of the interconnection elements between cells in very simple and space invariant, CNNs are suitable for VLSI implementation. In this paper, processing element of digital programmable CNN with variable template memory was implemented using CMOS circuit. CNN PE circuit was designe dto control gain for obtaining the optimal solutions in the CNN output. Performance of operation for 4*4 CNN circuit applied for fixed template and variable template analyzed with the result of simulation using HSPICE tool. As a result of simulations, the proposed variable template method verified to improve performance of operation in comparison with the fixed template method.

• Journal of Digital Contents Society
• /
• v.10 no.4
• /
• pp.633-637
• /
• 2009

In this paper, we present the reuse module library generating algorithm and register-transfer (RT) library generating algorithm considering the power consumption of reuse module for field-programmable gate array (FPGA) technology mapping in order to implement into the circuit for calculating power consumption. To realize the circuit of calculation of power consumption, the FPGA is selected. Considering lookup table (LUT) conditions of selected FPGA, technology mapping process is conducted to minimize the total power consumption. With these information, the circuit is realized using suitable given power consumption among allocated results of modules.

• Journal of Sensor Science and Technology
• /
• v.21 no.3
• /
• pp.235-239
• /
• 2012

This paper presents frequency response compensation technique, and a self-oscillation circuit for capacitive microresonator with the compensation technique using programmable capacitor array, to compensate for the frequency response distorted by parasitic capacitances, and to obtain stable oscillation condition. The parasitic capacitances between the actuation input port and capacitive output port distort the frequency response of the microresonator. The distorted non-ideal frequency response can be compensated using two programmable capacitor arrays, which are connected between anti-phased actuation input port and capacitive output port. The simulation model includes the whole microresonator system, which consists of mechanical structure, transimpedance amplifier with automatic gain control, actuation driver and compensation circuit. The compensation operation and oscillation output of the system is verified with the simulation results.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.10 no.5
• /
• pp.1-6
• /
• 1973

The paper deals with a study on an electronic watering device. The system is designed to scan 10 probes so that they detect moisture of soil. Input potentials are compared with reference level before the system is watering. rt provides a main clock oscillator and a control oscillator for the system control, and a programmable unijunction transistor is used for the control circuit. The reference levels are adjustable so as to water various soils. The device is tested for two different sails of moisture content ranging from 6 to 51%. It works at any input level higher than 0.6 V compared to the reference level.

• Journal of Advanced Navigation Technology
• /
• v.21 no.4
• /
• pp.386-393
• /
• 2017

Field programmable gate arrays (FPGAs) are widely used for verification in chip development. In order to verify the circuit programmed to the FPGA, data must be input to the FPGA. There are many ways to communicate with a chip through a PC and an external board, but the simplest and easiest way is to use a universal asynchronous receiver/transmitter (UART). Most recently, most circuits are designed to be internally connected to the advanced microcontroller bus architecture (AMBA) bus. In other words, to verify the designed circuit easily and simply, data must be transmitted through the AMBA bus through the UART. Also the AMBA bus has been available in various versions since version 4.0 recently. Advanced peripheral bus (APB) is suitable for simple testing. In this paper, we design a circuit for UART-to-APB interface. Circuits designed using Verilog-HDL were implemented in Altera Cyclone FPGAs and were capable of operating at speeds up to 380 MHz.