• Journal of electromagnetic engineering and science
• /
• v.1 no.2
• /
• pp.131-138
• /
• 2001

The DTV (Digital TV) tuner for an 8-VSB (Vestigial Side-Band) modulation was developed to meet the requirements of the ATSC (Advanced Television Systems Committee). The double frequency conversion and the active tracking filter in the front-end were used to cancel interferences between adjacent channels and multi-channels by suppressing the IF beat and the Image frequency. However, It was impossible to get frequency mapping between the tracking filter and the first VCO (Voltage Controlled Oscillator) in the existing DTV tuner structure which differs from the NTSC (National Television Systems Committee) tuner. This paper, therefore, suggests an assailable structure and a new method for the automatic frequency selection by mapping the frequency characteristics over the tracking voltage and the combined HW which is composed of a Micro-controller, an EEPROM (Electrically Erasable Programmable Read Only Memory), a DAC (Digital-to-Analog Converter), an OP amplifier, and a switch driver.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.14 no.11
• /
• pp.947-952
• /
• 2001

In this paper, a wideband SAW convolver using a parabolic horn waveguide was designed and its characteristics were investigated. The convolver was made with parabolic horn waveguide at compression ratio 9:1 for reducing propagation loss and for improving convolution efficiency between two input IDTs of center frequency 193.78 ㎒. The SAW convolver utilizing acoustic nonlinearities of piezoelectric material demonstrated that it can provide large S/N ratio and can be use for programmable matched filter(PMF) in spread spectrum communication system.

• Journal of Biosystems Engineering
• /
• v.33 no.5
• /
• pp.317-325
• /
• 2008

The electrocardiogram (ECG) measurement system consists of I/O interface to input the ECG signals from two electrodes, FPGA (Field programmable gate arrays) module to process the signal conditioning, and real time module to control the system. The algorithms based on wavelet transform were developed to remove the noise of the ECG signals and to determine the QRS-waves. Triangular wave tests were conducted to determine the optimal factors of the wavelet filter by analyzing the SNRs (signal to noise ratios) and RMSEs (root mean square errors). The hybrid rule, soft method, and symlets of order 5 were selected as thresholding rule, thresholding method, and mother wavelet, respectively. The developed wavelet filter showed good performance to remove the noise of the triangular waves with 10.98 dB of SNR and 0.140 mV of RMSE. The ECG signals from a total of 6 subjects were measured at different measuring postures such as lying, sitting, and standing. The durations of QRS-waves, the amplitudes of R-waves, the intervals of RR-waves were analyzed by using the finite impulse response (FIR) filter and the developed wavelet filter. The wavelet filter showed good performance to determine the features of QRS-waves, but the FIR filter had some problems to detect the peaks of Q and S waves. The measuring postures affected accuracy and precision of the ECG signals. The noises of the ECG signals were increased due to the movement of the subject during measurement. The results showed that the wavelet filter was a useful tool to remove the noise of the ECG signals and to determine the features of the QRS-waves.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.43 no.11 s.353
• /
• pp.175-184
• /
• 2006

In this paper, we describe a 900MHz CMOS RF transceiver using an ISM band for ZigBee applications. The architecture of the designed rx front-end, which consists of a low noise amplifier, a down-mixer, a programmable gain amplifier and a band pass filter. And the tx front-end, which consists of a band pass filter, a programmable gain amplifier, an up-mixer and a drive amplifier. A low-if topology is adapted for transceiver architecture, and the total current consumption is reduced by using a low power topology. Entire transceiver is verified by means of post-layout simulation and is implemented in 0.18um RF CMOS technology. The fabricated chip demonstrate the measured results of -92dBm minimum rx input level and 0dBm maximum tx output level. Entire power consumption is 32mW(@1.8VDD). Die area is $2.3mm{\times}2.5mm$ including ESD protection diode pads.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.4
• /
• pp.193-200
• /
• 2014

In this paper, the prototype of one-channel gamma-ray spectroscope for automatic radiopharmaceutical systhesis system was designed and characterized. The prototype employed CZT (CdZnTe) spear detector for gamma-ray detection and employed analog-type signal processing method. A radioactive sample Co-60 was used for measuring performance of the gamma-ray spectroscope and energy spectrum is gained with bandwidth of 1173keV. The analog board is made up of SF (shaping filter) and PHA (peak and hold amplifier) for shaping CZT output signal appropriately and ADC (analog to digital converter) and FPGA (field programmable gate array) for drawing gamma-ray spectrum by counting the digitalized gamma-ray signal data.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.46 no.4
• /
• pp.102-110
• /
• 2009

In this paper, we propose an object detection method for real-time in infrared (IR) images and PowerPC (PPC) and H/W design based on field programmable gate array (FPGA). An open H/W architecture has the advantages, such as easy transplantation of HW and S/W, support of compatibility and scalability for specification of current and previous versions, common module design using standardized design, and convenience of management and maintenance. Proposed background modeling for an open H/W architecture design decreases size of search area to construct a sparse block template of search area in IR images. We also apply to compensate for motion compensation when image moves in previous and current frames of IR sensor. Separation method of background and objects apply to adaptive values through time analysis of pixel intensity. Method of clutter reduction to appear near separated objects applies to median filter. Methods of background modeling, object detection, median filter, labeling, merge in the design embedded system execute in PFC processor. Based on experimental results, proposed method showed real-time object detection through global motion compensation and background modeling in the proposed embedded system.

• Journal of Korea Society of Industrial Information Systems
• /
• v.18 no.5
• /
• pp.15-18
• /
• 2013

This paper presents an analog front-end for electroencephalogram(EEG) signal processing. Since EEG signals are typically weak and located at very low frequencies, it is imperative to implement an amplifier with high gain, high common-mode rejection ratio(CMRR) and good noise immunity at very low frequencies. The analog front-end of this paper consists of a programmable-gain instrumentation amplifier and a band-pass filter. A frequency chopping technique is employed to remove the low-frequency noise. The circuits were fabricated in 0.18um CMOS technology and measurements showed that the analog front-end has the maximum gain of 60dB and >100dB CMRR over the programmable gain range.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.40 no.12
• /
• pp.2503-2510
• /
• 2015

This paper presents a single-phase energy measurement IC to measure electric power quantities. The entire IC includes two programmable gain amplifiers (PGAs), two ${\sum}{\Delta}$ modulators, a reference circuit, a low-dropout (LDO) regulator, a temperature sensor, a filter unit, a computation engine, a calibration control unit, registers, and an external interface block. The proposed energy measurement IC is fabricated with $0.18-{\mu}m$ CMOS technology and housed in a 32-pin quad-flat no-leads (QFN) package. It operates at a clock speed of 4,096 kHz and consumes 10 mW in 3.3 V supply.

• Journal of the Korea Society of Computer and Information
• /
• v.7 no.4
• /
• pp.115-120
• /
• 2002

This paper presents the implementation of IS-95 CDMA signal processor, baseband and Intermediate Frequency(IF) digital converter using Field Programmable Gate Array(FPGA) and ADC/DAC and frequency up/down converter IS-95 CDMA channel processor is generated the pilot channel signal with short PN code and Walsh-code generator. The digital If is composed of FPGA. digital transmit/receive signal processor and high speed analog-to-digital converter(ADC) and digital-to-analog converter(DAC). The frequency up/down converter consisted of filter, mixer, digital attenuator and PLL is analog conversion between intermediate frequency(IF) and baseband. This implemented system can be deployed in the IS-95 CDMA base station device etc.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.5 no.5
• /
• pp.427-434
• /
• 2000

The paper proposes a zero speed start-up scheme of direct rector controlled induction motor drive without any torque jerk. At standstill condition, a method is derived to calculate a stator flux with only stator current. The programmable 3-stage low pass filters with programmable time constants is used in order to solute the problem of integration for stator flux estimation in the direct vector control mode. Due to the time delay of 3-stage low pass filter, the status flux decreases rapidly and also the torque jerk occurs during the transition from standstill mode to the direct rector control mode. A feedforward control strategy of the stator flux is suggested to prevent the torque jerk at start-up. Through results of simulation and experiment with 32 bit DSP, the performance of the start-up scheme is verified.