• Korean Journal of Optics and Photonics
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• v.27 no.6
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• pp.212-217
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• 2016

In connection-oriented data-transport services, data loss can occur when the service experiences a problem on its end-to-end path. To promptly resolve this problem, the data-switching systems providing the service should quickly modify their internal configurations distributed among different places in each system. This is performed through a sequence of problem (event) recognition, sharing, and handling procedures among multiple control processors in the system. This paper proposes a method for event sharing and messaging between control processors, to improve the time determinacy of event processing. This method simplifies runtime event sharing and minimizes the time variability caused by the event data, resulting in a decrease in the latency time in processing global events. The proposed method lessens the latency time of global event processing by about 40%, compared to general methods, for 738 internal path changes.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.5
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• pp.916-924
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• 2003

Fair queueing has been an important issue in the multimedia networks where resources are shared among nodes both wired and wireless. In most fair queuing algorithms, based on the generalized processor sharing(GPS), emphasizes fairness guarantee while overlooking bounded delay guarantee which is critical to support multimedia services in the networks. In this paper, we propose a new fair queueing scheme, delay guaranteed fair queueing (DGFQ), which guaranteeing bounded delay of flows according to their individual delay requirements for multimedia services in the wireless packet networks.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.951-954
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• 2002

This paper presents the implementation of hash functions for IPSEC chip. There is an increasing interest in high-speed cryptographic accelerators for IPSec applications such as VPNs (virtual private networks). Because diverse algorithms are used in Internet, various hash algorithms are required for IPSec chip. Therefore, we implemented SHA-1, HAS-160 and MD5 in one chip. These hash algorithms are designed to reduce the number of gates. SHA-1 module is combined with HAS-160 module. As the result, the required logic elements are reduced by 27%. These hash algorithms have been implemented using Altera's EP20K1000EBC652-3 with PCI bus interface.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.1049-1052
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• 1999

We present a use. interface(UI) simulator for developing a mobile phone. This simulator consists of 3 major modules: Graphic Tool Editor, User Interface Software(UI), and Network Command Processor(NCP). The Graphic Tool Editor can design a virtual mobile terminal. The NCP sends a command to the phone and then receives its status from the phone after completion of the command. We can add or modify lots of features easily to the phone using the UI module. These modules can interact each other by sharing the common area in the memory. By doing so, these modules can exchange their status and data to operate in real-time. We have designed and tested a virtual prototyping phone for the LGP 3200 manufactured by LGIC by using the simulator. Through a series of experiment, we have believed that our virtual prototyping interactive simulator can do shorten its development and testing cycle by applying it in the early design phase.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.8
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• pp.2033-2042
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• 1996

In this papre, we describe a recently implemented echo canceller for digital cellular communication of Code Division Multiple Access(CDMA) that features time sharing of digital signal processor(DSP) over four channels in one DSP to reduce per channel costs. In the Public Land Mobile Network(PLMN), it is important to cancel the echo reflected from the Public Switched Telephone Network(PSTN) side. In case of digital mobile system, the round-trip delay of the echo is in excess of about 180 milliseconds due to frame-by-frame voice coding. It is necessary to cancel the echo in PLMN. We have developed a multi-channel echo canceller tht operates with Time Switch Module in a Mobile Switching Center(MSC). The general echo canceller needs PCM trunk interface circuits and the tone detection and disabling circuits, but the multi-channel echo canceller linked with Time Switch Module does not need them. Therefore we could develop the effective and economical echo canceller.

• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.30-32
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• 2000

내적을 계산하는데 있어서 Distributed Arithmetic(DA)을 사용하면 곱셈기를 사용하는 것보다 소비전력 및 크기를 효율적으로 줄일 수 있고, 고속동작이 가능한 회로구현이 쉽기 때문에 신호처리 시스템 설계에 많이 사용하고 있다. DA에는 롬-기반 DA와 가산기-기반 DA를 이용한 방법이 있는데, 가산기-기반 DA는 Sharing property와 계수의 Spare non-zero bit property를 최대한 이용하여 설계가 가능하기 때문에 크기 및 동작속도 측면에서 효율적인 구현이 가능하다. 본 논문에서는 가산기-기반 DA의 이러한 특성을 최대한 이용하여 멀티미디어 신호처리에 적합한 DCT/IDCT 프로세서를 설계하였고 다른 구조 및 롬-기반 DA와 비교 평가해본 결과 크기 및 속도 측면에서 효율적인 결과를 얻었다.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04a
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• pp.148-150
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• 2003

본 논문에서는 인터넷 종단 호스트에서 공유 자원의 대역폭 제약조건과 종료시한 제악조건 모두를 만족시킬 수 있는 자원 할당 구조를 제안한다. 제안된 구조는 두 단계로 구성된다. 상위 단계에서는 비례 분배 스케줄러(proportional share scheduler)인 EFT-C/D (Earliest Finish Time Credit/Debit) 스케줄러가 수행된다. 이 스케줄러는 CPU와 같은 시분할 공유 자원을 하위 단계 스케줄러들에게 지정된 비율로 분배하는 역할을 한다. 그리고 하위 단계에서는 서로 다른 시간 제약조건이 부여된 태스크들을 스케줄링 하기위해 다양한 실시간 스케줄러가 수행된다. 본 연구의 주요 성과는 두 가지로 요약된다. 첫째, 이상적인 GPS (Generalized Processor Sharing) 서버와 거의 동등한 수준으로 자원을 공평하게 분배하는 EFT-C/D 알고리즘을 개발하였다. 둘째, 하위 단계에서 수행되는 EDF 스케줄러에 대해 이용율(utilization)에 기반한 스케룰링 가능성 분석 방법을 개발하였다. 이 방법은 주어진 태스크 집합에 대해 단순히 이용율만을 계산하여 스케줄링 가능성을 판별할 수 있다. 따라서 새로운 태스크가 생성될 때 수락 여부를 시스템 수행 중에 제어할 수 있는 장점이 있다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.250-252
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• 2017

블록암호 국제표준 AES(Advanced Encryption Standard), 국내표준 ARIA(Academy, Research Institute, Agency) 및 국제표준 해시함수 Whirlpool을 통합 하드웨어로 구현하였다. ARIA 블록암호와 Whirlpool 해시함수는 AES와 유사한 구조를 가지며, 본 논문에서는 저면적 구현을 위해서 하드웨어 자원을 공유하여 설계하였다. Verilog-HDL로 설계된 ARIA-AES-Whirlpool 통합 보안 프로세서를 Virtex5 FPGA로 구현하여 정상 동작함을 확인하였고, $0.18{\mu}m$ 공정의 CMOS 셀 라이브러리로 합성한 결과 20 MHz의 동작 주파수에서 71,872 GE로 구현되었다.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.608-611
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• 2003

A large part of the embedded system, compared with the PC, have low performance CPU and small memory. So the embedded operating system fits the condition of that hardware system. A Single Address Space (SAS) OS has the operating system and all applications in the single address space. The SAS architecture enhances sharing and co-operation, because addresses have a unique interpretation. Thus, pointer-based date structures can be directly communicated and shared between programs at any time, and can be stored directly on storage. The key point of the SAS OS on the embedded system is the low overhead inter-action between programs in process and usage. So SAS OS can be ported on the low performance CPU. In this paper, we design the SAS OS (named emNOS, Embedded Network Operating System) on the ARMTTDMI processor. Finally we show the benefits of the SAS OS on the embedded system.

• Journal of the Korea Society for Simulation
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• v.10 no.3
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• pp.59-70
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• 2001

Typical low-level image processing tasks require thousands of operations per pixel for each input image. Traditional general-purpose computers are not capable of performing such tasks in real time. Yet important features of traditional computers are not exploited by low-level image processing tasks. Since storage requirements are limited to a small number of low-precision integer values per pixel, large hierarchical memory systems are not necessary. The mismatch between the demands of low-level image processing tasks and the characteristics of conventional computers motivates investigation of alternative architectures. The structure of the tasks suggests employing an array of processing elements, one per pixel, sharing instructions issued by a single controller. In this paper we implemented various image processing filtering using the format converter. Also, we realized from conventional gray image process to color image process. This design method is based on realized the large processor-per-pixel array by integrated circuit technology This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware.