• Journal of Broadcast Engineering
• /
• v.13 no.4
• /
• pp.452-462
• /
• 2008

In this paper, we address issues associated with the real-time implementation of the MPEG-1/2 Layer-II (or MUSICAM) and MPEG-4 ER-BSAC decoders for Digital Multimedia Broadcasting (DMB) on TMS320C64x+ that is a fixed-point DSP processor with a clock speed of 330 MHz. To achieve the real-time requirement, they should be optimized in different steps as follows. First of all, a C-code level optimization is performed by sharing the memory, adjusting data types, and unrolling loops. Next, an algorithm level optimization is carried out such as the reconfiguration of bitstream reading, the modification of synthesis filtering, and the rearrangement of the window coefficients for synthesis filtering. In addition, the C-code of a synthesis filtering module of the MPEG-1/2 Layer-II decoder is rewritten by using the linear assembly programming technique. This is because the synthesis filtering module requires the most processing time among all processing modules of the decoder. In order to show how the real-time implementation works, we obtain the percentage of the processing time for decoding and calculate a RMS value between the decoded audio signals by the reference MPEG decoder and its DSP version implemented in this paper. As a result, it is shown that the percentages of the processing time for the MPEG-1/2 Layer-II and MPEG-4 ER-BSAC decoders occupy less than 3% and 11% of the DSP clock cycles, respectively, and the RMS values of the MPEG-1/2 Layer-II and MPEG-4 ER-BSAC decoders implemented in this paper all satisfy the criterion of -77.01 dB which is defined by the MPEG standards.

• Journal of KIISE:Computing Practices and Letters
• /
• v.13 no.4
• /
• pp.231-239
• /
• 2007

This paper presents the trade-off relationship between area and performance in the hardware design space exploration for the Korean national standard 128-bit block cipher algorithm SEED. In this paper, we compare the following four hardware design types of SEED algorithm : (1) Design 1 that is 16 round fully pipelining approach, (2) Design 2 that is a one round looping approach, (3) Design 3 that is a G function sharing and looping approach, and (4) Design 4 that is one round with internal 3 stage pipelining approach. The Design 1, Design 2, and Design 3 are the existing design approaches while the Design 4 is the newly proposed design in this paper. Our new design employs the pipeline between three G-functions and adders consisting of a F function, which results in the less area requirement than Design 2 and achieves the higher performance than Design 2 and Design 3 due to pipelining and module sharing techniques. We design and implement all the comparing four approaches with real hardware targeting FPGA for the purpose of exact performance and area analysis. The experimental results show that Design 4 has the highest performance except Design 1 which pursues very aggressive parallelism at the expanse of area. Our proposed design (Design 4) shows the best throughput/area ratio among all the alternatives by 2.8 times. Therefore, our new design for SEED is the most efficient design comparing with the existing designs.

• Korea Journal of Hospital Management
• /
• v.15 no.3
• /
• pp.143-169
• /
• 2010

This is a case study of Seoul St. Mary's Hospital applying a real-time enterprise (RTE) strategy to improve customer satisfaction and operational efficiency with the main process of medical institutions. The hospital is applying an RTE strategy to get real-time information on occurrences at each contact point of the main process of the medical institution from reservation to discharge through dashboard and to resolve issues through rapid decision-making. The RTE strategy of the hospital has some summaries: First, the hospital has linked a hospital management strategy to the RTE strategy to build a patient-centered treatment process. Second, the hospital has operated a control tower for change management and implementation monitoring in the process of implementing the RTE strategy. Third, the hospital has built systematic RTE-based environment as an application program in which the nU System is linked to Business Processor Renovation (BPR) promoted from 2006 on. Fourth, the hospital is applying a strategy to improve efficiency in operating the hospital by increasing customer satisfaction, removing inefficiency and variability, and managing medical resources efficiently through the RTE strategy. Fifth, it has established an information-sharing system through authority management for each user in terms of RTE information. Sixth, it has supplemented limitations of short-term information of the RTE strategy by linking the key performance index to the cost information system in order to improve performance of the RTE strategy. Seventh, it has improved customer satisfaction and achieved higher performance in improving operational efficiency, as compared with rival hospitals, through the RTE strategy.

• The KIPS Transactions:PartA
• /
• v.15A no.1
• /
• pp.61-68
• /
• 2008

In this paper, we propose the VLSI design of Multi-Format Video Decoder (MFD) to support video codec standards such as MPEG-2, MPEG-4, H.264 and VC-1. The target of the proposed MFD is the Full HD (High Definition) video processing needed for the high-end D-TV SoC (System-on-Chip). The size of the design is reduced by sharing the common large-size resources such as the RISC processor and the on-chip memory among the different codecs. In addition, a detachable architecture is introduced in order to easily add or remove the codecs. The detachable architecture preserves the stability of the previously designed and verified codecs. The size of the design is about 2.4 M gates and the operating clock frequency is 225MHz in the Samsung 65nm process. The proposed MFD supports more than Full-HD (1080p@30fps) video decoding, and the largest number of video codec standards known so far.

• Journal of KIISE:Information Networking
• /
• v.32 no.2
• /
• pp.254-260
• /
• 2005

In the guaranteed service, a real-time scheduling algorithm must achieve both high level of network utilization and scalable implementation. Here, network utilization indicates the number of admitted real-time sessions. Unfortunately, existing scheduling algorithms either are lack of scalable implementation or can achieve low network utilization. For example, scheduling algorithms based on time-stamps have the problem of O(log N) scheduling complexity where N is the number of sessions. On the contrary, round-robin algorithms require O(1) complexity. but can achieve just a low level of network utilization. In this paper, we propose a scheduling algorithm that can achieve high network utilization without losing scalability. The proposed algorithm is a Hierarchical Round-Robin (H-RR) algorithm that utilizes multiple rounds with different interval sizes. It provides latency bounds similar to those by Packet-by-Packet Generalized Processor Sharing (PGPS) algorithm using a sorted-Priority queue. However, H-RR requires a constant time for implementation.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.6 no.1
• /
• pp.34-42
• /
• 2001

A battery is the device that transforms the chemical energy into the direct-current electrical energy directly without a mechanical process. Unit cells are connected in series to obtain the required voltage, while being connected in parallel to organize capacity for load current and to decrease the internal resistance for corresponding the sudden shift of the load current. Because the voltage droop down in one set of battery is faster than in tow one, it amy result in the low efficiency of power converter with the voltage drop and cause the system shutdown. However, when the system being driven in parallel, a circular-current can be generated. The changing current differs in each set of battery because the system including batteries, rectifiers and loads is connected in parallel and it makes the charge voltage constant. It is shown that, as a result the new batteries are heated by over-charge and over-discharge, and the over charge current increases rust of the positive grid and consequently shortens the lifetime of the new batteries. The difference between the new batteries and old ones is the amount of internal resistance. In this paper, we can detect the unbalance current using the micro-processor and achieve the balance current by adjusting resistance of each set. The internal resistance of each set becomes constant and the current of charge and discharge comes to be balanced by inserting the external resistance into the system and calculating the change of internal resistance.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2014.05a
• /
• pp.574-577
• /
• 2014

Multimedia contents sharing services based on DLNA (Digital Living Network Alliance) technology such as Allshare or Smartshare in wireless home networks is widely adapted in Korea. However, the characteristics of the wireless network - frequently fluctuated bandwidth and signal strength could degrade the quality perceived by users. To minimize the impact of the challenge there are active researches in dynamic adaptive streaming. This paper proposes a dynamic adaptive streaming approach designed in a wireless network taking into account of the specifications of the user device such as resolution and processor. We modify the Kalman filter considering the characteristics of the device and demonstrate that the proposed approach determines Bit Rate using the modified filter.

• Journal of Internet of Things and Convergence
• /
• v.6 no.4
• /
• pp.81-87
• /
• 2020

This paper creates a standard node for acquiring sensor data from various industrial sensors (IoT/non-IoT) for the establishment of Smart Factory Digital Twin, and provides inter-compatible data by linking zones by group/process to secure data stability and to ensure the digital twin (Digital Twin) of Smart Factory. The process of the Zone Master platform contains interface specifications to define sensor objects and how sensor interactions between independent systems are performed and carries out individual policies for unique data exchange rules. The interface for execution control of the Zone Master Platform processor provides system management, declaration management for public-subscribe, object management for registering and communicating status information of sensor objects, ownership management for property ownership sharing, time management for data synchronization, and data distribution management for Route information on data exchange.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.17 no.3
• /
• pp.699-707
• /
• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.43 no.4 s.310
• /
• pp.123-132
• /
• 2006

In this paper, the digital video and audio system is improved so that various digital video data formats in DVD disc, and digital audio data formats through the S/PDIF ports may be decoded. It is not easy to implement all decoding functions of video and audio by a DVD processor. The special structure in audio decoding circuit is proposed in this system so as to have simultaneously almost same video and audio performance in quality. By dividing the decoding circuit separately into video and audio part, the audio quality can be dramatically improved together with supporting several audio formats and with several effects. In order to satisfy the perfect audio system to support to audio decoding formats, it is just enough to get the expensive, complicated decoder. However, it may be not easy to get this expensive decoder in near future. Therefore it is rather to adopt the downloading method by which the host should download the appropriate code into memory by detecting the corresponding audio bit streams. It is proved that this method may be efficient in the point of sharing resource of audio data for video decoding.