• The Transactions of the Korea Information Processing Society
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• v.2 no.4
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• pp.499-508
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• 1995

Domain Analysis is an activity to identify commonalities and variabilities which similar application areas in order to reuse analyzed information easily in new software construction. Most of domain analysis output is represented by various diagrams without common standard, and its manual reuses result in low reusability. Domain analysis language can be used to represent domain analysis information and make it possible to automate reuse and test the specifications. In this paper we designed and implemented a processor to reuse domain analysis information represented by domain analysis language and applied our approach to a rental domain and got new specification instances. In addition, we compared reuse of a data flow diagramming tool with reuse of a domain information processor and found combining and found combining of each approach can increase the reusability of both.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.12
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• pp.704-715
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• 2004

Recently, a single or multi processor system uses the hierarchical memory structure to reduce the time gap between processor clock rate and memory access time. A cache memory system includes especially two or three levels of caches to reduce this time gap. Moreover, one of the most important things In the hierarchical memory system is the hit rate in level 1 cache, because level 1 cache interfaces directly with the processor. Therefore, the high hit rate in level 1 cache is critical for system performance. A victim cache, another high level cache, is also important to assist level 1 cache by reducing the conflict miss in high level cache. In this paper, we propose the advanced high level cache management scheme based on the processor reuse information. This technique is a kind of cache replacement policy which uses the frequency of processor's memory accesses and makes the higher frequency address of the cache location reside longer in cache than the lower one. With this scheme, we simulate our policy using Augmint, the event-driven simulator, and analyze the simulation results. The simulation results show that the modified processor reuse information scheme(LIVMR) outperforms the level 1 with the simple victim cache(LIV), 6.7% in maximum and 0.5% in average, and performance benefits become larger as the number of processors increases.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.465-472
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• 2017

Security has become one of the most important requirements for various devices for multi-sensor based embedded systems. The AES (Advanced Encryption Standard) algorithm is widely used for security, however, it requires high computing power. In order to reduce the CPU power for the data encryption of images, we propose a new image encryption module using hardware memoization, which can reuse previously generated data. However, as image pixel data are slightly different each other, the reuse rate of the simple memoization system is low. Therefore, we further apply an approximate concept to the memoization system to have a higher reuse rate by sacrificing quality. With the novel technique, the throughput can be highly improved by 23.98% with 14.88% energy savings with image quality loss minimization.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.658-661
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• 2003

In multimedia database system, it is very important issue how to query multimedia data and present the result of query. Also, in order to reuse the query result in other applications, multimedia database system must be considered to provide the query result which is more generalized form. This paper includes the design and implementation of MMSQL query processor. MMSQL query processor provides the presentation of query result which is SMIL document. Therefore, MMSQL query result in this paper can be use to variant multimedia applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.31-37
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• 2006

Low-density parity-check (LDPC) codes are recently emerged due to its excellent performance. The standard for European high definition satellite digital video broadcast, DVB-S2 has adopted LDPC codes as a channel coding scheme. This paper proposes a DVB-S2 LDPC decoder architecture using a hybrid parity check matrix which is efficient in hardware implementation for both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the hybrid H-matrix scheme, the architecture of LDPC decoder for DVB-S2 can be very practical and efficient. In addition, we show a new Variable Node processor Unit (VNU) architecture to reuse the VNU for various code rates and optimized block memory placement to reuse. We design a DVB-S2 LDPC decoder of code rate 1/2 usng the proposed architecture. We estimate the performance of the DVB-S2 LDPC decoder and compare it with other decoders.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.52-58
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• 2013

Replacement policy is one of the key factors determining the effectiveness of a cache. The LRU replacement policy has remained the standard for caches for many years. However, the traditional LRU has ineffective performance in zero-reuse line intensive workloads, although it performs well in high temporal locality workloads. To address this problem, We propose a new replacement policy; DCR(Dynamic Counter based Replacement) policy. A temporal locality of workload dynamically changes across time and DCR policy is based on the detection of these changing. DCR policy improves cache miss rate over a traditional LRU policy, by as much as 2.7% at maximum and 0.47% at average.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04b
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• pp.1285-1288
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• 2002

Bluetooth wireless technology is a publicly available specification proposed for Radio Frequency (RF) communication for short-range and point-to- multipoint voice and data transfer. It operates in the 2.4GHz ISM(Industrial, Scientific and Medical) band and offers the potential for low-cost, broadband wireless access for various mobile and portable devices at range of about 10 meters. In this paper, we describe the structure and the test results of the bluetooth baseband module we have developed. This module was developed based on IP reuse. So Interface of each module such as link controller UART, and audio CODEC is designed based on ARM7 comfortable processor. We also considered various interfaces of related external chips. The fully synthesizable baseband module was fabricated in a $0.25{\mu}m$ CMOS technology occupying $2.79{\times}2.8mm^2$ area including the ARM TDMI processor. And a FPGA implementation of this module is tested for file and bit-stream transfers between PCs.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.4 s.310
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• pp.55-65
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• 2006

Most of fast block motion estimation algorithms reported so far in literatures aim to reduce the computation in terms of the number of search points, thus do not fit well with multimedia processors due to their irregular data flow. For multimedia processors, proper reuse of data is more important than reducing number of absolute difference operations because the execution cycle performance strongly depends on the number of off-chip memory access. Therefore, in this paper, we propose a Hexagon-shape line search (HEXSLS) algorithm using line search pattern which can increase data reuse from on-chip local buffer, and check sub-sampling points in line search pattern to reduce unnecessary SAD operation. Our experimental results show that the prediction error (MAE) performance of the proposed HEXSLS is similar to that of the full search block matching algorithm (FSBMA), while compared with the hexagon-based search (HEXBS), the HEXSLS outperforms. Also the proposed HEXSLS requires much lesser off-chip memory access than the conventional fast motion estimation algorithm such as the hexagon-based search (HEXBS) and the predictive line search (PLS). As a result, the proposed HEXSLS algorithm requires smaller number of execution cycles on media processor.

• Journal of KIISE:Computing Practices and Letters
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• v.9 no.2
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• pp.213-225
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• 2003

In multimedia database system, it is very important issue how to query multimedia data and present the result of query. Also, in order to reuse the query result in other applications, multimedia database system must be considered to provide the query result which is more generalized form. In this paper, I propose a presentation model for presenting query result in multimedia database system and MMSQL based on the developed model for processing multimedia database query. This paper includes the design and implementation of MMSQL query processor. MMSQL query processor provides the presentation of query result which is SMIL (Synchronized Multimedia Integration Language) document. Therefore, MMSQL query result in this paper can be use to variant multimedia applications.

• KIPS Transactions on Computer and Communication Systems
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• v.9 no.1
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• pp.1-8
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• 2020

The thermal image device support image to detect infrared light from the object without light. It can use not only defence-related industry, but also civilian industry. This paper presents a new thermal image processing module using common image processor. The proposed module shows 10~20% performance improvement with normal mode and 50% performance improvement with sleep mode compared with the previously thermal image module based FPGA. and it guarantees high scalability according to modular system. In addition, the proposed module improves modulation and reuse, so it expect to have reduction of development period, low development cost. various application. In addition, it expect to have satisfaction of customer requirements, development design, development period, release date of product.