• 전자공학회논문지 IE
• /
• v.48 no.3
• /
• pp.20-25
• /
• 2011

We developed a method of accelerating the operation speed of communication systems for SDR(Software Defined Radio) systems in WiBro environment. In this paper, we propose a new scheme of using GPU(Graphics Processing Unit) for implementing the communication system which perform with the functionality of SDR. In general, communication systems is made by DSP(Digital Signalling Processor) or FPGA(Field Programmable Gate Array). However, in this case, there are exist the problem of implementation and debugging caused by each CPU characteristic. The GPU is optimized for vector processing because it usually consists of multiple processors and each processor in GPU is composed of a set of threads. We also developed Framework to use GPU and CPU resources effectively for reducing the operation time. From the various simulation, it is confirmed that GPU system have good performance in WiBro system.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.17 no.6
• /
• pp.161-167
• /
• 2017

Recently, small radar has been reduced in size and power consumption to cope with various operating environments. It also requires the development of a small millimeter wave radar with high range resolution to disable the system of target with a single strike. In this paper, we design and implement a signal processor that can be used in small millimeter wave radar. The signal processor for the small millmeter wave radar is designed with a digital IF(Intermediate Frequency) receiver and DFT(Discrete Fourier Transform) module capable of real time FFT operation for miniaturization and low power consumption. Also it was to leverage the FPGA(Field Programmable Gate Array) and DAC(Digital Analog Converter) as a means for correcting the distortion of signals that can occur in the receive path of the small millimeter wave radar to create a RF signal that is used by the system. Finally, we verified the signal processor presented through performance test

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2017.10a
• /
• pp.621-622
• /
• 2017

In this paper, a low-complexity FFT processor is proposed for narrow-band interference signal cancellation based array antenna. The proposed FFT pocessor can support the variable length of 64, 128 and 512. By reducing number of non-tirval multipliers with mixed radix-4/2/4/2/4/2 algorithm and flexible multi-path delay commutator(MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased. The proposed FFT processor was designed in Xilinx system generator and Implemented with Xilinx Virtex-7 FPGA. With the proposed architecture, the number of slices for the processor is 11454, and the number of DSP48s is 194.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2021.05a
• /
• pp.600-602
• /
• 2021

With the development of the mobile industry and growing interest in artificial intelligence (AI) technology, a lot of research for AI processors which applicable to embedded systems is under study. When implementing AI to embedded systems, the design should be considered the restriction of resource and power consumption. Moreover, it is efficient to include a dedicated hardware accelerator in order to complement the low computational performance of the embedded system. In this paper, we propose an stand-alone embedded AI processor. The proposed AI processor includes a hardware accelerator that is dedicated to the distance-based AI algorithm and a general-purpose MCU that supports flexible programmability for application to various embedded systems. The AI processor was designed with Verilog HDL and verified by implementing on Field Programmable Gate Array (FPGA).

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.30B no.1
• /
• pp.1-9
• /
• 1993

In recent days high perfermance graphic operation is needed, since computer graphics is widely used for computer-aided design and simulator using high resolution graphic card. In this paper a graphic accelerator is designd with the functions of graphic primitives generation and geometrical transformations. 1-D Systolic Array Processor for Matris Vector operation is designed and used in main ALU of a graphic accelerator, since these graphic algorithms have comonon operation of Matris Vector. Conclusively, in case that the resolution of graphic domain is 800$\times$600, and 33.3nsec operator is used in a graphic accelerator, 29732 lines per second and approximately 6244 circles per second is generated.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.31B no.5
• /
• pp.1-11
• /
• 1994

In computer graphics since objects atre constructed by lines and curves, the high-speed curve generator is indispensible for computer aided design and simulatation. Since the functions of graphic generation can be represented as a series of matrix operations, in this paper, two kind of the high-speed Bezier curve generator that uses matrix equation and a recursive relation for Bezier polynomials are designed. And B-spline curve generator is designed using interdependence of B-spline blending functions. As the result of the comparison of designed curve generator and reference [5], [6] in the operation time and number of operators, the curve generator with 1-dimensional systolic array processor for matrix vector operation that uses matrix equation for Bezier curve is more effective.

• Journal of the Korea Society of Computer and Information
• /
• v.4 no.4
• /
• pp.94-100
• /
• 1999

This paper concerns the implementation of a digital neural network which performs the high speed operation of Hopfield model's arithmetic operation. It is also designed to use a look-up table and produce floating point arithmetic of nonlinear function with high speed operation. The arithmetic processing of Hopfleld is able to describe the matrix-vector operation, which is adaptable to design the array processor because of its recursive and iterative operation .The proposed method is expected to be applied to the field of real neural networks because of the realization of the current VLSI techniques.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.631-632
• /
• 2006

In this paper, acquiring the more desirable to adopt design SoC for the fast hierarchical motion estimation, we exploit foreground and background search algorithm (FBSA) base on the dual arithmetic processor element(DAPE). It is possible to estimate the large search area motion displacement using a half of number PE in general operation methods. And the proposed architecture of MHME improve the VLSI design hardware through the proposed FBSA structure with DAPE to remove the local memory. The proposed FBSA which use bit array processing in search area can improve structure as like multiple processor array unit(MPAU).

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.10C
• /
• pp.999-1007
• /
• 2002

In this paper, the operation of matched filter for searching initial synchronization in direct sequence spread spectrum receiver is studied. The implementation model of the matched filter by HDL (Hardware Description Language) is proposed. The model has an architecture based on parallelism and pipeline for fast processing, which includes circular buffer, multiplier, adder, and code look-up table. The performance of the model is analyzed and compared with the implementation by a conventional digital signal processor. It is implemented on a FPGA (Field Programmable Gate Array) and its operation is validated in a timing simulation result.

• Journal of the Korea Institute of Military Science and Technology
• /
• v.9 no.2 s.25
• /
• pp.111-117
• /
• 2006

This paper describes the design principles and methods of electronic processor for thermal imager with 320$\times$240 staring array infrared detector. For the detector's nonuniformity correction and excellent image quality, we have designed the multi-point correction method using the defocusing technique of the optics. And to enhance the image of low contrast and improve the detection capability, the new technique of histogram processing has been designed. Through these image processing techniques, we have developed the high quality thermal imager and acquired a satisfactory thermal image. The result of MRTD(Minimum Resolvable Temperature Difference) is $0.1^{\circ}C$ at 4cycles/mard.