• International Journal of Control, Automation, and Systems
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• v.1 no.2
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• pp.252-256
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• 2003

A biped robot should be designed to be an effective mechanical structure and have smaller hardware system if it is to be a stand-alone structure. This paper shows the design methodology of a biped robot controller using FPGA(Field Programmable Gate Array). A hardware system consists of DSP(Digital Signal Processor) as the main CPU, and FPGA as the motor controller. By using FPGA, more flexible hardware system has been achieved, and more compact and simple controller has been designed.

• Journal of Advanced Marine Engineering and Technology
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• v.38 no.8
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• pp.1000-1003
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• 2014

There are 70 vertical and 70 horizontal correctors for Pohang Light Source. Until mid of 2000, power supplies for these correctors were based on 1990's technology, so the global orbit feedback system was not possible with poor 12 bit resolution. A new task force team was assembled to develop new power supplies with BESSY type DAC cards. After the project, two vertical correctors in each lattice were connected with new power supplies, and the global orbit feedback was available within the accuracy of 5 microns. However, this replacement was not enough to satisfy the beam stability requirement of 2 microns for PLS. We have launched another power supply design based on all digital technology. This attempt was completed within a year, and 80 units were assembled in house. Currently, the global orbit feedback system is running successfully with new digital power supplies and the compensation of chamber motion due to the thermal load by using digital displacement transducers attached on each BPMs.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.6
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• pp.67-76
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• 1997

In radar signal processing, an A/D converter with sufficient dynamic range and high sampling speed is required to detect the weakest target signals in heavy clutter and ECM environments. As the sampling frequency increases, the amount of digital data transfered to the signal processing module is also increased. To overcome these massive data transfer burden, we need an A/D conversion module with an enough data transfer rate. In this paper, we proposed an implementation scheme of a new A/D conversio module that can be used in multi-mode 3-D phased array radar signal processing system, and evaluated the performance. The proposed A/D conversion module is implemented with a standard A/D converter and a 6U-standard VME bus.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.7
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• pp.465-472
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• 2004

Analog CPPN-based optimal road boundary detection algorithm for autonomous vehicle is proposed. The CPPN is a massively connected analog parallel array processor. In the paper, the dynamic programming which is an efficient algorithm to find the optimal path is implemented with the CPPN algorithm. If the image of road-boundary information is utilized as an inter-cell distance, and goals and start lines are positioned at the top and the bottom of the image, respectively, the optimal path finding algorithm can be exploited for optimal road boundary detection. By virtue of the parallel and analog processing of the CPPN and the optimal solution of the dynamic programming, the proposed road boundary detection algorithm is expected to have very high speed and robust processing if it is implemented into circuits. The proposed road boundary algorithm is described and simulation results are reported.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.1
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• pp.129-139
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• 2013

In this paper, we proposed a new hardware architecture for calculating digital holograms at high speed, and verified it with field programmable gate array (FPGA). First, we rearranged memory scheduling and algorithm of computer generated hologram (CGH), and then introduced pipeline technique into CGH process. Finally we proposed a high-performance CGH processor. The hardware was implemented for the target of FPGA, which calculates a unit region of holograms, and it was verified using a hardware environment of NI Inc. and a FPGA of Xilinx Inc. It can generate a hologram of $16{\times}16$ size, and it takes about 4 sec for generating a hologram of a $1,024{\times}1,024$ size, using 6K point sources.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1551-1554
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• 2002

In this paper, the hardware implementation of the RSA public-key cryptographic algorithm is presented. The RSA cryptographic algorithm is depends on the computation of repeated modular exponentials. The Montgomery algorithm is used and modified to reduce hardware resources and to achieve reasonable operating speed for smart card. An efficient architecture for modular multiplications based on the array multiplier is proposed. We have implemented a 10240it RSA cryptographic processor based on proposed scheme in IESA system developed for smart card emulating system. As a result, it is shown that proposed architecture contributes to small area and reasonable speed for smart cards.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.9
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• pp.712-718
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• 1991

In this paper, we propose a graphic system for high speed generation of bitmap font data from the outline font data such as PostScript, etc. In desk-top publishing system. A VLSI chip called KAFOG was designed for the high-speed calculation of a cubic Bezier curve, which was implemented in 1.5\ulcorner CMOS gate array using 17,000 gates. A cubic Bezier curve is approximated by a set of line segments in KAFOG at the throughput of 250K curves per second with the clock frequency of 40 MHz. A prototype graphic system was developed using two MC6800 microprocessors and the KAFOG chip. Two microprocessors cooperate in a master and slave mode, and handshaking is used for communication between two processors. KAFOG chip, being controlled by the slave processor, operates as a coprocessor for the calculation of the outline font. The throughput of the prototype graphic system is 40 64$\times$64 outline fonts per sencond.

• Proceedings of the KIEE Conference
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• summer
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• pp.1471-1473
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• 2004

Maximum power point tracking(MPPT) is used in photovoltaic(PV) systems to maximize the photovoltaic array output power, irrespective of the temperature and irradiation conditions. The object of this paper is to compare and analyze MPPT efficiency for different MPPT techniques by changing irradiance. Also, this paper introduces transformerless grid-connected inverter. Simple flow charts and characteristics of each MPPT algorithm are shown. The implementation of transformerless grid-connected inveter system was based on a digital signal processor(DSP). Simulation was carried out for each MPPT method.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.223-225
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• 2007

본 논문에서는 FPGA(Field Programmable Gate Array) 기반의 전류 제어기를 설계하고 구현하였다. 기존의 DSP (Digital Signal Processor) 기반의 전류 제어기는 알고리즘 연산으로 인해 일반적으로 한 샘플링의 디지털 시지연이 발생한다. 반면에, FPGA 기반의 전류제어기는 FPGA의 높은 연산 능력을 이용하여, 알고리즘 연산에 필요한 시간을 감소시킬 수 있다. 이는 시지연이 물리적으로 줄기 때문에, 어떠한 시지연 보상 알고리즘 없이 전류 제어기의 대역폭을 향상시킬 수 있다. 구현된 FPGA 기반의 전류 제어기의 성능은 실험을 통해 검증되었다.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.242-243
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• 2017

기존 Digital Signal Processor (DSP)를 사용하여 높은 동작 주파수의 LLC 공진형 컨버터를 구동하는 경우 낮은 동작 주파수 분해능과 계산 속도에 의해 출력 전압 제어성능과 동특성에 한계가 생긴다. 이를 해결하기 위해 기존의 분해능 및 계산 속도 부족에 의한 영향을 분석하고 Field Programmable Gate Array (FPGA)를 설계하여 높은 동작 주파수 분해능 및 동특성을 얻고자 제안한다. FPGA를 이용한 성능향상을 DSP (TI - TMS 38335)와 FPGA (Xilinx XC7A100T)를 사용하여 비교 분석하고자 한다.