• 전자공학회논문지A
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• 제30A권3호
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• pp.114-129
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• 1993

A FFT array processor algorithm and architecture which anc use a minumum required number of simple, duplicate multiplier-adder processing elements according to various computation speed, will be presented. It is based on the p fold symmetry in the radix p constant geometry FFT butterfly stage with shuffled inputs and normally ordered outputs. Also, a methodology to implement a high performance high radix FFT with VLSI by constructing a high radix processing element with the duplications of a simple lower radix processing element will be discussed. Various performances and the trade-off between computation speed and hardware complexity will be evaluated and compared. Bases on the presented architecture, a radix 2, 8 point FFT processing element chip has been designed and it structure and the results will be discusses.

• 전자공학회논문지A
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• 제31A권4호
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• pp.127-135
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• 1994

In this paper we propose an EWLD(Enhanced Weighted Levenshtein Distance) algorithm to organize code-string pattern matching linear array processor based on the mappting to an one-dimensional array from a two-dimensional matching matrix, and design a processing element(PE) of the processor, N PEs are required instead of NS02T in the processor because of the mapping. Data input and output between PEs and all internal operations of each PE are performed in bit-serial fashion. The bit-serial operation consists of the computing of word distance (WD) by comparison and the selection of optimal code transformation path, and takes 22 clocks as a cycle. The layout of a PE is designed based on the double metal $1.5\mu$m CMOS rule. About 1,800 transistors consistute a processing element and 2 PEs are integrated on a 3mm$\times$3mm sized chip.

• 정보보호학회논문지
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• 제10권4호
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• pp.3-11
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• 2000

본 논문에서는 몽고메리 알고리즘을 사용하여 모듈러 곱셈을 빠르게 수행하는 선형 시스톨릭 어레이를 설계하고, 이 곱셈기와 LR 이진 제곱 곱셈 알고리즘을 사용하여 n 비트 메시지 블록에 대해 모듈러 지수 연산을 수행하는 지수 연산 프로세서를 설계한다 이 프로세서는 제어장치, 입출력 시프트 레지스터, 지수 연산 장치 등 3개의 영역으로 나 누어진다. 설계된 지수 연산 프로세서의 동작을 검증하기 위해 VHDL를 사용하여 모델링하고 MAX+PLUS II를 사용하여 시뮬레이션 한다. 메시지 블록의 길이 n=512일 때 설계된 지수 연산 프로세서의 지연 시간은 59.5ms이다. 설계된 모듈러 지수 연산 프로세서는 RSA 칩(chip)에 이용될 수 있을 것이다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.14-16
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• 1988

With the development of VLSI technology, research on special processors for high-speed processing is on the increase and studies are focused on designing VLSI-oriented processors for signal processing. This paper processes a one-dimensional systolic array for Discrete Hartley Transform implementation and also processes processing element which is well described for algorithm. The discrete Hartley Transform(DHT) is a real-valued transform closely related to the DFT of a real-valued sequence can be exploited to reduce both the storage and the computation requried to produce the transform of real-valued sequence to a real-valued spectrum while preserving some of the useful properties of the DFT is something preferred. Finally, the architecture of one-dimensional 8-point systolic array, the detailed diagram of PE, total time units concept on implementation this arrays, and modularity are described.

• 전기전자학회논문지
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• 제24권3호
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• pp.797-802
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• 2020

본 논문에서는 base-4 시스토릭 어레이 FFT 프로세서에서 사용되는 여러 메모리를 하나의 메모리로 공유함으로써 기존 보다 작은 메모리 면적의 FFT 프로세서의 설계 및 구현 결과를 제시한다. 메모리를 공유하여 면적이 줄어드는 장점이 생겼으며, 데이터의 입출력이 하나의 메모리에서 진행되므로 데이터의 흐름이 단순해졌다. 제시한 FFT 프로세서를 FPGA 디바이스 상에서 구현 및 검증하였으며, 구현 결과 4096-point FFT 기준 51,855개의 CLB LUT, 29,712개의 CLB registers, 8개의 block RAM tile과 450개의 DSP로 구현되었고, 최대 동작 주파수는 150MHz 인 것을 확인했으며 특히, 기존 base-4 시스토릭 어레이 구조 대비 메모리 면적이 65% 감소 가능함을 확인하였다.

• 전자공학회논문지B
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• 제33B권2호
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• pp.149-158
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• 1996

In this paper we describe designing and implementing a digital neural chip and a parallel neural machine for simulating large scale neural netsorks. The chip is a single-chip multiprocessor which has four digiral neural processors (DNP-II) of the same architecture. Each DNP-II has program memory and data memory, and the chip operates in MIMD (multi-instruction, multi-data) parallel processor. The DNP-II has the instruction set tailored to neural computation. Which can be sed to effectively simulate various neural network models including on-chip learning. The DNP-II facilitates four-way data-driven communication supporting the extensibility of parallel systems. The parallel neural machine consists of a host computer, processor boards, a buffer board and an interface board. Each processor board consists of 8*8 array of DNP-II(equivalently 2*2 neural chips). Each processor board acn be built including linear array, 2-D mesh and 2-D torus. This flexibility supports efficiency of mapping from neural network models into parallel strucgure. The neural system accomplishes the performance of maximum 40 GCPS(giga connection per second) with 16 processor boards.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.1503-1506
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• 1987

This paper proposes the self test method for 16 point FFT processor with systolic array architecture. To test efficiently and solve the increased hardware problems due to built-in self test, we change the normal registers into Linear Feedback Shift Registers(LFSR). LFSR can be served as a test pattern generator or a signature analyzer during self test operation, while LFSR a ordering register or a accumulator during normal operation. From the results of logic simulation for 16 point FFT processor by YSLOG, the total time is estimated in about. 21.4 [us].

• 한국마린엔지니어링학회:학술대회논문집
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• 한국마린엔지니어링학회 2006년도 전기학술대회논문집
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• pp.249-250
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• 2006

In this paper, hardware design and implementation of digital controller for the High Precision Digital Power Supply (HPDPS) based on Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA) is presented. Developed digital controller is composed of high resolution Digital Pulse Width Modulation (DPWM) and high resolution analog to digital converter circuit with anti-aliasing filter. And Digital Signal Processor (DSP) has the capability of a few micro-second calculation time for one feedback loop. 32-bit DSP and DPWM with 150[ps] step resolution is used to implement the HPDPS. Also 18-bit 2 mega sample per second ADC board is adopted for the developed digital controller. Also, hardware structure of the developed digital controller and experimental results of the first prototype board for HPDPS is described.

• 전기전자학회논문지
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• 제27권4호
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• pp.624-629
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• 2023

본 논문에서는 ESPRIT(estimation of signal parameters via rotational invariance techniques)알고리듬 기반 재구성 가능한 각도 추정기를 제안 및 설계하였다. ESPRIT은 배열 안테나(uniform linear array)의 천이불변(shift invariance) 성질을 이용해 배열 안테나에 도래하는 신호의 도래각을 추정하는 알고리듬이다. 하지만 여전히 ESPRIT 알고리즘은 공분산 행렬, 고윳값 분해 등 높은 복잡도를 가지는 연산을 필요로 하므로 실시간 도래각 추정을 위해 하드웨어 프로세서로 구현이 필요하다. ESPRIT에서 성능은 안테나 개수와 관련이 있으며, 응용에 따라 요구되는 안테나 수는 상이할 수 있다. 이에 본 논문에서는 응용되는 분야에 따라 성능을 높이고 연산 복잡도 문제를 시킬 수 있도록 2 ~ 8개의 가변 안테나 개수를 지원하는 ESPRIT 프로세서를 제안하였다. 또한, 제안된 ESPRIT 프로세서는 MI-ESPRIT 구조를 기반으로 배열 안테나의 다중 불변성을 활용하여 성능을 향상시켰으며, 최소자승법 알고리즘을 간소화 시켜 복잡도를 감소시켰다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.269-272
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• 2001

In this paper we proposed the format converter design and implementation for real time image processing. This design method is based on realized the large processor-per-pixel array by integrated circuit technology in which this two types of integrated structure is can be classify associative parallel processor and parallel process with DRAM cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilized the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start