• Title/Summary/Keyword: Processing verification

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New Approach to Verification in Security Protocol by using Fuzzy Algorithm (퍼지 알고리즘을 이용한 보안 프로토콜 검증)

  • 신승중;박인규
    • Proceedings of the Korea Database Society Conference
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    • 2000.11a
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    • pp.343-349
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    • 2000
  • The objective of this paper was to cope with the verification of the message transfer protocol that integrates the electronic signature and the distribution and authentication of public key in TCP/IP using Choquet fuzzy integral compapred with fuzzy integral. They were classified into the security technology, the security policy, the electronic document processing, the electronic document transportation and the encryption and decryption keys in its function. The measures of items of the message security protocol were produced for the verification of the implemented document in every function.

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Efficient Simulation Acceleration by FPGA Compilation Avoidance (FPGA 컴파일 회피에 의한 효과적인 시뮬레이션 가속)

  • Shim, Kyu-Ho;Park, Chang-Ho;Yang, Sei-Yang
    • The KIPS Transactions:PartA
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    • v.14A no.3 s.107
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    • pp.141-146
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    • 2007
  • In this paper, we proposed an efficient FPGA-based simulation acceleration method based on FPGA compilation avoidance, which can effectively decrease the long debugging turnaround time incurred from the every debugging process in the functional verification. The proposed method had been experimentally applied to the functional verification for a microcontroller design. It had clearly shown that the debugging turnaround time was greatly reduced while the high simulation speed of the simulation acceleration was still maintained.

A Study on the Signature Verification Feature by Statistical Analysis (통계적 분석에 의한 서명 특징정보에 관한 연구)

  • Kim, Jin-whan;Cho, Jae-hyun
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2009.05a
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    • pp.865-867
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    • 2009
  • This paper is a research on the statistical analysis of the feature information for the dynamic signature verification. we could improved processing time and reduce signature database without increase of error rate. We have used statistical analysis method T-test for the verification based on the experimental results.

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DESIGN OF COMMON TEST HARNESS SYSTEM FOR SATELLITE GROUND SEGMENT DEVELOPMENT

  • Seo, Seok-Bae;Kim, Su-Jin;Koo, In-Hoi;Ahn, Sang-Il
    • Proceedings of the KSRS Conference
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    • 2007.10a
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    • pp.544-547
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    • 2007
  • Because data processing systems in recent years are more complicated, main function of the data processing is divided as several sub-functions which are implemented and verified in each subsystem of the data processing system. For the verification of data processing system, many interface tests among subsystems are required and also a lot of simulation systems are demanded. This paper proposes CTHS (Common Test Harness System) for satellite ground segment development which has all of functions for interface test of the data processing system in one PC. Main functions of the CTHS software are data interface, system log generation, and system information display. For the interface test of the data processing system, all of actions of the CTHS are executed by a pre-defined operation scenario which is written by purpose of the data processing system test.

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Software-based Real-time GNSS Signal Generation and Processing Using a Graphic Processing Unit (GPU)

  • Im, Sung-Hyuck;Jee, Gyu-In
    • Journal of Positioning, Navigation, and Timing
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    • v.3 no.3
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    • pp.99-105
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    • 2014
  • A graphic processing unit (GPU) can perform the same calculation on multiple data (SIMD: single instruction multiple data) using hundreds of to thousands of special purpose processors for graphic processing. Thus, high efficiency is expected when GPU is used for the generation and correlation of satellite navigation signals, which perform generation and processing by applying the same calculation procedure to tens of millions of discrete signal samples per second. In this study, the structure of a GPU-based GNSS simulator for the generation and processing of satellite navigation signals was designed, developed, and verified. To verify the developed satellite navigation signal generator, generated signals were applied to the OEM-V3 receiver of Novatel Inc., and the measured values were examined. To verify the satellite navigation signal processor, the performance was examined by collecting and processing actual GNSS intermediate frequency signals. The results of the verification indicated that satellite navigation signals could be generated and processed in real time using two GPUs.

Test of a Multilayer Dose-Verification Gaseous Detector with Raster-Scan-Mode Proton Beams

  • Lee, Kyong Sei;Ahn, Sung Hwan;Han, Youngyih;Hong, Byungsik;Kim, Sang Yeol;Park, Sung Keun
    • IEIE Transactions on Smart Processing and Computing
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    • v.4 no.5
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    • pp.297-304
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    • 2015
  • A multilayer gaseous detector has been developed for fast dose-verification measurements of raster-scan-mode therapeutic beams in particle therapy. The detector, which was constructed with eight thin parallel-plate ionization chambers (PPICs) and polymethyl methacrylate (PMMA) absorber plates, is closely tissue-equivalent in a beam's eye view. The gas-electron signals, collected on the strips and pad arrays of each PPIC, were amplified and processed with a continuous charge.integration mode. The detector was tested with 190-MeV raster-scan-mode beams that were provided by the Proton Therapy Facility at Samsung Medical Center, Seoul, South Korea. The detector responses of the PPICs for a 190-MeV raster-scan-mode proton beam agreed well with the dose data, measured using a 2D ionization chamber array (Octavius model, PTW). Furthermore, in this study it was confirmed that the detector simultaneously tracked the doses induced at the PPICs by the fast-oscillating beam, with a scanning speed of 2 m s-1. Thus, it is anticipated that the present detector, composed of thin PPICs and operating in charge.integration mode, will allow medical scientists to perform reliable fast dose-verification measurements for typical dynamic mode therapeutic beams.

An Off-line Signature Verification Using PCA and LDA (PCA와 LDA를 이용한 오프라인 서면 검증)

  • Ryu Sang-Yeun;Lee Dae-Jong;Go Hyoun-Joo;Chun Myung-Geun
    • The KIPS Transactions:PartB
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    • v.11B no.6
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    • pp.645-652
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    • 2004
  • Among the biometrics, signature shows more larger variation than the other biometrics such as fingerprint and iris. In order to overcome this problem, we propose a robust offline signature verification method based on PCA and LDA. Signature is projected to vertical and horizontal axes by new grid partition method. And then feature extraction and decision is performed by PCA and LDA. Experimental results show that the proposed offline signature verification has lower False Reject Rate(FRR) and False Acceptance Rate(FAR) which are 1.45% and 2.1%, respectively.

A study on The Design of Embedded Network Module for Web-based Remote Verification and proofreading (웹기반 원격 검.교정 시스템을 위한 임베디드 네트워크 모듈 설계에 대한 연구)

  • Kim, Min-Geun;Lee, Sang-Hun;Lee, Hyuek-Jae
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2007.06a
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    • pp.83-86
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    • 2007
  • The necessity of the high speed exclusive use server that connect digital measure instrument flag to internet and CPU use rate of measure flag uses other imbedded operating system with many general servers to verification & proofreading system in remotion. This research is objective that embody high speed network module for Site-Based remote verification & proofreading system and through internet digital measure instrument flag to remote verification & proofreading, TCP/IP Offload Engine processing and improved that is Imbedded TCP/IP stack for high speed networking.

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A study on Verification Process for LRT's Power Supply System Based on the ISO/IEC 15288 (국제표준 ISO/IEC 15288 기반의 경량전철 전력시스템 검증 프로세스에 관한 연구)

  • Choi, Won Chan;Bae, Joon Ho;Heo, Jae Hun;Lee, Sang Geun;Han, Seok Youn
    • Journal of the Korean Society of Systems Engineering
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    • v.9 no.1
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    • pp.47-53
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    • 2013
  • The object of this study is to define systematically for outputs of Verification Process among the system life cycle process based on ISO/IEC 15288 for power supply system, which is one of the importance sub-systems to configure the LRT system. Furthermore, to prevent various problem in advance that can occur in the Transition LRT's power supply to be completed Integration. For this purpose, traceability of verification requirement and outputs. should be managed to use verification for system requirement and data processing tool. by system engineering techniques of system life cycle process based on ISO/IEC 15288 to LRT system.

Formal Verification of Embedded Java Program (임베디드 자바 프로그램의 정형 검증)

  • Lee, Tae-Hoon;Kwon, Gi-Hwon
    • The KIPS Transactions:PartD
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    • v.12D no.7 s.103
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    • pp.931-936
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    • 2005
  • There may be subtle errors in embedded software since its functionality is very complex. Thus formal verification for detecting them is very needed. Model checking is one of formal verification techniques, and SLAM is a well-known software model checking tool for verifying safety properties of embedded C program. In this paper, we develop a software model checker like SLAM for verifying embedded Java program Compared to SLAM, our tool allows to verify liveness properties as well as safety ones. As a result, we verify some desired properties in embedded Java program for controlling REGO robot.