Browse > Article
http://dx.doi.org/10.3745/KIPSTA.2007.14-A.3.141

Efficient Simulation Acceleration by FPGA Compilation Avoidance  

Shim, Kyu-Ho (부산대학교 대학원 컴퓨터공학과)
Park, Chang-Ho (동양시스템즈 IT서비스운영팀)
Yang, Sei-Yang (부산대학교 컴퓨터공학과)
Publication Information
The KIPS Transactions:PartA / v.14A, no.3, 2007 , pp. 141-146 More about this Journal
Abstract
In this paper, we proposed an efficient FPGA-based simulation acceleration method based on FPGA compilation avoidance, which can effectively decrease the long debugging turnaround time incurred from the every debugging process in the functional verification. The proposed method had been experimentally applied to the functional verification for a microcontroller design. It had clearly shown that the debugging turnaround time was greatly reduced while the high simulation speed of the simulation acceleration was still maintained.
Keywords
Verification; Simulation; Simulation acceleration; FPGA;
Citations & Related Records
연도 인용수 순위
  • Reference
1 N. Kim, H. Choi, S. Lee, S. Lee, I. Park, and C. Kyung, 'VIrtual Chip Making Functional Models Work on Real Target Systems,' in Proc. of 35th DAC, pp.170-173, June 1998
2 Xilinx ISE 6 Software Manuals, Xilinx Inc. (http:///www.xilinx.com), 2004
3 ModelSim SE User's Manual, Mentor Graphics (http://www.model.com), 2006
4 Stuart Swan, 'SystemC Transaction Level Models and RTL Verification', in Proc. of 43rd DAC, pp.90-92, July 2006   DOI
5 Richard Foster, 'A Design Style to Simplify IP integration and Verification,' White paper, VLSI Technology, Inc. (http://www.vlsi.com), 1999
6 'Cadence Emulation Simulation Acceleration', White paper, Cadence Design Systems Inc. (http://www.cadence.com) , 2002
7 Murali Kudlugi, Saha Hassoun, Charles Selvidge, Duaine Pryor, 'A Transaction-Based Unified Simulation Emulation Architecture for Functional Verification', in Proc. of 38th DAC, pp.623-628, June 2001   DOI
8 Daniel P. Bovet, Marco Cesati, Understanding the Linux Kernel, O'REILLY Publishers, December 2002
9 Alessandro Rubini,· Jonathan Corbet, Linux Device Drivers, O'REILLY Publishers, June 2001
10 IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language, IEEE Std. 1364-1995
11 Swapnajit Mittra, Principles of Verilog PLI, Kluwer Academic Publishers, 2000
12 JTAG Boundary Scan, IEEE Std. 1149.1
13 Spartan-If $200^{TM}$ PCI Development Board User's Guide V2.0, Memec (http://www.memec.com). 2002
14 Synplify Pro User Guide, Synplicity Inc. (http://www.synplicity.com). 2005
15 김남도, 양세양, '초고속 시스템 에뮬레이터의 구조와 이를 위한 소프트웨어', 한국정보처리학회논문지 A, 1598-2831, 제8A권 4호, pp.479-488, 2001   과학기술학회마을