• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.10a
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• pp.56-59
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• 1997

The recent machine tools are requested so high-quality processing and productivity increasing. Therefore it is so necessary to develop technology for high-speed and high-precision. This thesis touches on the development of high speed and intellectual line center. At first, the line center is necessary that strong structure, compact structure an light weight design for high-speed processing and transfer. So. It is necessary that examination of new materials and structures for light-weight and control devices for precision processing. So. it si going to make mention of the process of 1st model production for the above-mentioned base on test model production and evaluation.

• Journal of the Korea Society of Computer and Information
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• v.10 no.5 s.37
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• pp.109-114
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• 2005

Twofish cryptographic algorithm is concise algorithm itself than Rijndael cryptographic algorithm as AES, and easy of implementation is good, but the processing speed has slow shortcoming. Therefore this paper designed improved MDS block to improve Twofish cryptographic algorithm's speed. Problem of speed decline by a bottle-neck Phenomenon of the Processing speed existed as block that existing MDS block occupies Twofish cryptosystem's critical path. To reduce multiplication that is used by operator in MDS block this Paper removed a bottle-neck phenomenon and low-speed about MDS itself using LUT operation and modulo-2 operation. Twofish cryptosystem including modified MDS block designed by these result confirmed that bring elevation of the processing speed about 10$\%$ than existing Twofish cryptosystem.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.7 no.4
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• pp.96-103
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• 1998

With the advance of processing technology , so as to spare fuel, piston heads used in automobile reciprocating engine have complex 3-dimension, with respect to shape such as ovality, profile, eccentricity, offset, recess. Therefore, coming out of the existing process work used master cam. the process work is performed using a CNC lathe. For a precision processing, the processing work is need to make study of high speed feed gear synchronized with the rotative speed of main spindle. And then the high speed feeding system must maintain high dynamic stiffness, high speed and high positioning accuracy . In this paper, in order to achieve high speed cutting tool feeding. The linear brushless DC motor is used for satisfying this process work. The ball bush and turicite is used as the guidance of the feed gear system. Also linear encoders, digital servo amplifiers and controller are used for controlling driving motor. This paper presents the design and simulation of the new tool feed system for noncircular machining.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.10 s.340
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• pp.35-38
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• 2005

Treatise that see designed MDS block newly algorithm itself is concise and improve the speed of Twofish cryptographic algorithm that easy of implement is good but the processing speed has slow shortcoming than Rijndael cryptographic algorithm Problem of speed decline by a bottle-neck phenomenon of processing process existed as block that designed MDS block occupies critical path of Twofish cryptographic system Multiplication arithmetic that is used by operator in this MDS convex using LUT arithmetic and modulo-2 arithmetic speed decline and a bottle-neck phenomenon about MDS itself remove. Twofish cryptographic system including MDS block designed newly by these result confirmed that bing elevation of the processing speed about $10\%$ than existing Twofish cryptographic system.

• Journal of the Korea Society of Computer and Information
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• v.10 no.3 s.35
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• pp.183-188
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• 2005

Parallel processing in block cryptographic algorithm is difficult, because Feistel structure that is basis structure of block cryptographic algorithm is sequential processing structure. Therefore this paper changes these sequential processing structure and Feistel structure made parallel processing to be possible. This paper that apply this modified structure designed DES that have parallel Feistel structure. Proposed parallel Feistel structure could prove greatly block cryptographic algorithm's performance such as DES and so on that could not but have trade-off relation the data processing speed and data security interval because block cryptographic algorithm can not use pipeline method because of itself structural problem. Therefore, modified Feistel structure is going to display more superior security function and processing ability of high speed than now in case apply way that is proposed to SEED, AES's Rijndael, Twofish etc. that apply Feistel structure.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.2
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• pp.178-184
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• 2004

In this paper, we designed an image processing system for the high speed line-scan camera which adopts the new memory model we proposed. As a resolution and a data rate of the line-scan camera are becoming higher, the faster image processing systems are needed. But many conventional systems are not sufficient to process the image data from the line-scan camera during a very short time. We designed the memory controller which eliminates the time for transferring image data from the line-scan camera to the main memory with high-speed SRAM and has a dual-port configuration therefore the DSP can access the main memory even though the memory controller are writing the image data. The memory controller is implemented by VHDL and Xilinx SPARTAN-IIE FPGA.

• The Transactions of the Korea Information Processing Society
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• v.1 no.1
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• pp.99-104
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• 1994

This paper proposes the method to process many pattern data 2-dimensionally at high speed in designing the physical of LSI. And this study shows that the switching network,which transmits pattern data between memory and processing elements at high speed on bidirection,has been designed using the barrel shifter and simulated with VHDL design system.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.3
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• pp.114-129
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• 1993

A FFT array processor algorithm and architecture which anc use a minumum required number of simple, duplicate multiplier-adder processing elements according to various computation speed, will be presented. It is based on the p fold symmetry in the radix p constant geometry FFT butterfly stage with shuffled inputs and normally ordered outputs. Also, a methodology to implement a high performance high radix FFT with VLSI by constructing a high radix processing element with the duplications of a simple lower radix processing element will be discussed. Various performances and the trade-off between computation speed and hardware complexity will be evaluated and compared. Bases on the presented architecture, a radix 2, 8 point FFT processing element chip has been designed and it structure and the results will be discusses.

• Journal of the Semiconductor & Display Technology
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• v.11 no.3
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• pp.39-44
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• 2012

Electronics in modern lives have become more miniaturized and precise. Multi Layered Ceramic Capacitor (MLCC) occupies 50% of electronic components consisting of electronics. This high volume of the production needs high speed and more precise machine performances. The dominate parts of the production equipments are the module transporting components and the visual inspection module. Most visual inspection has been off-line because of the image processing time. In this paper, a new image processing method is proposed to reduce thousands of matrix calculation for image processing and realize on-line high speed inspection.

• Annual Conference of KIPS
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• 2021.11a
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• pp.446-448
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• 2021

In training a deep learning model, it is crucial to tune various hyperparameters and gain speed and accuracy. While hyperparameters that mathematically induce convergence impact training speed, system parameters that affect host-to-device transfer are also crucial. Therefore, it is important to properly tune and select parameters that influence the data loader as a system parameter in overall time acceleration. We propose an automated framework called Num Worker Tuner (NWT) to address this problem. This method finds the appropriate number of multi-processing subprocesses through the search space and accelerates the learning through the number of subprocesses. Furthermore, this method allows memory efficiency and speed-up by tuning the system-dependent parameter, the number of multi-process spawns.