• Title/Summary/Keyword: Process variation of offset

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A Study on the Design of a ROIC for Uncooled Infrared Ray Detector Using Differential Delta Sampling Technique (차동 델타 샘플링 기법을 이용한 비냉각형 적외선 검출회로의 설계에 관한 연구)

  • Jung, Eun-Sik;Kwan, Oh-Sung;Lee, Po;Jeong, Se-Jin;Sung, Man-Young
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.24 no.5
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    • pp.387-391
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    • 2011
  • A uncooled infrared ray sensor used in an infrared thermal imaging detector has many advantages. But because the uncooled infrared ray sensor is made by MEMS (micro-electro-mechanical system) process variation of offset is large. In this paper, to solve process variation of offset a ROIC for uncooled infrared ray sensor that has process variation of offset compensation technique using differential delta sampling and reference signal compensation circuit was proposed. As a result of simulation that uses the proposed ROIC, it was possible to acquire compensated output characteristics without process variation of offsets.

Effects of Offset Gate on Programing Characteristics of Triple Polysilicon Flash EEPROM Cell

  • Kim, Nam-Soo;Choe, Yeon-Wook;Kim, Yeong-Seuk
    • Journal of Electrical Engineering and information Science
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    • v.2 no.3
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    • pp.132-138
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    • 1997
  • Electrical characteristics of split-gate flash EEPROM with triple polysilicon is investigated in terms of effects of floating gate and offset gate. In order to search for t the effects of offset gate on programming characteristics, threshold voltage and drain current are studied with variation of control gate voltage. The programming process is believed to depend on vertical and horizontal electric field as well as offset gate length. The erase and program threshold voltage are found to be almost constant with variation of control gate voltage above 12V, while endurance test indicates degradation of program threshold voltage. With increase of offset gate length, program threshold voltage becomes smaller and the drain source voltage just after program under constant control gate voltage becomes higher.

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Self-aligned Offset Gated Poly-Si TFTs by Employing a Photo Resistor Reflow Process (Photo Resistor Reflow 방법을 이용한 오프셋 마스크를 이용하지 않는 새로운 자기 정합 폴리 실리콘 박막 트랜지스터)

  • Park, Cheol-Min;Min, Byung-Hyuk;Han, Min-Koo
    • Proceedings of the KIEE Conference
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    • 1995.07c
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    • pp.1085-1087
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    • 1995
  • A large leakage current may be one of the critical issues for poly-silicon thin film transistors(poly-Si TFTs) for LCD applications. In order to reduce the leakage current of poly-Si TFTs, several offset gated structures have been reported. However, those devices, where the offset length in the source region is not same as that in the drain region, exhibit the asymmetric electrical performances such as the threshold voltage shift and the variation of the subthreshold slope. The different offset length is caused by the additional mask step for the conventional offset structures. Also the self-aligned implantation may not be applicable due to the mis-alignment problem. In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photo resistor reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate from both sides of the main gate. The poly-Si channel layer below the offset oxide is protected from the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of our new device is the offset lesion due to the offset oxide. Our experimental results show that the offset region, due to the photo resistor reflow process, has been successfully obtained in order to fabricate the offset gated poly-Si TFTs. The advantages of the proposed device are that the offset length in the source region is the same as that in the drain region because of the self-aligned implantation and the proposed device does not require any additional mask process step.

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Design of a 1.2V 7-bit 800MSPS Folding-Interpolation A/D Converter with Offset Self-Calibration (Offset Self-Calibration 기법을 적용한 1.2V 7-bit 800MSPS Folding-Interpolation A/D 변환기의 설계)

  • Kim, Dae-Yun;Moon, Jun-Ho;Song, Min-Kyu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.3
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    • pp.18-27
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    • 2010
  • In this paper, a 1.2V 7-bit 1GSPS A/D converter with offset self-calibration is proposed. The proposed A/D converter structure is based on the folding-interpolation whose folding rate is 2, interpolation rate is 8. Further, for the purpose of improving the chip performance, an offset self-calibration circuit is used. The offset self-calibration circuit reduce the variation of the offset-voltage,due to process mismatch, parasitic resistor, and parasitic capacitance. The chip has been fabricated with a 1.2V 65nm 1-poly 6-metal CMOS technology. The effective chip area is $0.87mm^2$ and the power dissipates about 110mW at 1.2V power supply. The measured SNDR is about 39.1dB when the input frequency is 250MHz at 800MHz sampling frequency. The measured SNDR is 3dB higher than the same circuit without any calibration.

Vision chip for edge detection with a function of pixel FPN reduction (픽셀의 고정 패턴 잡음을 감소시킨 윤곽 검출용 시각칩)

  • Suh, Sung-Ho;Kim, Jung-Hwan;Kong, Jae-Sung;Shin, Jang-Kyoo
    • Journal of Sensor Science and Technology
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    • v.14 no.3
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    • pp.191-197
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    • 2005
  • When fabricating a vision chip, we should consider the noise problem, such as the fixed pattern noise(FPN) due to the process variation. In this paper, we propose an edge-detection circuit based on biological retina using the offset-free column readout circuit to reduce the FPN occurring in the photo-detector. The offset-free column readout circuit consists of one source follower, one capacitor and five transmission gates. As a result, it is simpler and smaller than a general correlated double sampling(CDS) circuit. A vision chip for edge detection has been designed and fabricated using $0.35\;{\mu}m$ 2-poly 4-metal CMOS technology, and its output characteristics have been investigated.

A Study on a Dual Electromagnetic Sensor System for Weld Seam Tracking of I-Butt Joints

  • Kim, J.-W.;Shin, J.-H.
    • International Journal of Korean Welding Society
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    • v.2 no.2
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    • pp.51-56
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    • 2002
  • The weld seam tracking system for arc welding process uses various kinds of sensors such as arc sensor, vision sensor, laser displacement sensor and so on. Among the variety of sensors available, electro-magnetic sensor is one of the most useful methods especially in sheet metal butt-joint arc welding, primarily because it is hardly affected by the intense arc light and fume generated during the welding process, and also by the surface condition of weldments. In this study, a dual-electromagnetic sensor, which utilizes the induced current variation in the sensing coil due to the eddy current variation of the metal near the sensor, was developed for arc welding of sheet metal I-butt joints. The dual-electromagnetic sensor thus detects the offset displacement of weld line from the center of sensor head even though there's no clearance in the joint. A set of design variables of the sensor was determined far the maximum sensing capability through the repeated experiments. Seam tracking is performed by correcting the position of sensor to the amount of offset displacement every sampling period. From the experimental results, the developed sensor showed the excellent capability of weld seam detection when the sensor to workpiece distance is near less than 5 ㎜, and it was revealed that the system has excellent seam tracking ability for the I-butt joint of sheet metal.

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A Study of a Dual-Electromagnetic Sensor for Automatic Weld Seam Tracking (용접선 자동추적을 위한 이중 전자기센서의 개발에 관한 연구)

  • 신준호;김재응
    • Journal of Welding and Joining
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    • v.18 no.4
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    • pp.70-75
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    • 2000
  • The weld seam tracking system for arc welding process uses various kinds of sensors such as arc sensor, vision sensor, laser displacement and so on. Among the variety of sensors available, electro-magnetic sensor is one of the most useful methods especially in sheet metal butt-joint arc welding, primarily because it is hardly affected by the intense arc light and fume generated during the welding process, and also by the surface condition of weldments. In this study, a dual-electromagnetic sensor, which utilizes the induced current variation in the sensing coil due to the eddy current variation of the metal near the sensor, was developed for arc welding of sheet metal butt-joints. The dual-electromagnetic sensor thus detects the offset displacement of weld line from the center of sensor head even though there's no clearance in the joint. A set of design variables of the sensor were determined for the maximum sensing capability through the repeated experiments. Seam tracking is performed by correcting the position of sensor to the amount of offset displacement every sampling period. From the experimental results, the developed sensor showed the excellent capability of weld seam detection when the sensor to workpiece distance is near less than 5 mm, and it was revealed that the system has excellent seam tracking ability for the butt-joint of sheet metal.

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Design of Readout IC for Uncooled Infrared Bolometer Sensor using Bias Offset Correction Technique (오프셋 보정 기술을 이용한 비냉각형 적외선 센서용 신호검출 회로 설계)

  • Park, Sang-Won;Hwang, Sang-Joon;Hong, Seung-Woo;Jung, Eun-Sik;Sung, Man-Young
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2005.07a
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    • pp.23-25
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    • 2005
  • Infrared bolometer sensor's variation is detected by voltage drop between reference resistor and bolometer resistor in this architecture. One of the serious problems in this architecture is that these resistors value has a process variation. So common-mode level could be different from expectation in room temperature. Different common-mode level could lead to wrong output at the end of readout circuit. We suggest useful method to solve this problem. Difference correction using capacitor has reduced CM level difference to 86% for 1 $M\Omega$. bolometer and reference resistor's 10% variation.

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The Variation of Offset Ink Properties according to the Vegetable Oil Estersr (Vegetable Oil Esters에 따른 Offset 잉크의 물성 변화에 관한 연구)

  • Park, Jung-Min;Kim, Sung-Bin
    • Journal of the Korean Graphic Arts Communication Society
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    • v.30 no.1
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    • pp.1-19
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    • 2012
  • According as gradually increasing the demand for eco-friendly at the printing process, it has been progressed fairly development. Especially, the inks are used by soy oil beginning of ink industry for preventing environment, it is possible to make eco-friendly inks with vegetable ester. So it is not necessary to use petroleum-based solvents at all for preventing environment. These eco-friendly inks have a benefits they are able to use the renewable resource. But basically vegetable oils have that reduce the VOC(Volatile Organic Compound) and high viscosity, high solubility properties. So if the vegetable oils use in the ink, set off problem occur on the paper because of slow drying time. In case of vegetable ester, it has similar the molecular weight and kinetic viscosity with hydrocarbon solvent, it is able to control the power of dilution about the resin. So, it has benefit that solve the problem of the existing eco-friendly inks. In this study, different types of ester were made by six types of vegetable oils and used ester in the varnishes and inks properties are comparison with hydrocarbon solvent based ink. By considering the intrinsic properties of vegetable oil, ester used to analyze the changes in ink properties, using ester varnish is applied to study the rheology characteristics and emulsification with inks.

A Study on the Identification of Cutter Offset by Cutting Force Model in Milling Process (밀링가공에서 절삭력 모델을 이용한 커터 오프셋 판별에 관한 연구)

  • 김영석
    • Journal of the Korean Society of Manufacturing Technology Engineers
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    • v.7 no.2
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    • pp.91-99
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    • 1998
  • This paper presents a methodology for identifying the cutter runout geometry in end milling process. Cutter runout is common but undesirable phenomenon in multi-tooth machining because it introduces variable chip loading to insert which results in a accelerated tool wear. amplification of force variation and hence enlargement vibration amplitude From understanding of chip load change kinematics, the analytical cutting force convolution model was formulated as the angular domain convolution model was formulated as the angular domain convolution of three dynamic cutting force component functions. By virtue of the convolution integration property, the frequency domain expression of the local cutting forces and the chip width density of the cutter. Experimental study is presented to validate the analytical model. This study provides the in-process monitoring and compensation of dynamic cutter runout to improve machining tolerance and surface quality for industrial application.

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