• 한국산업정보학회:학술대회논문집
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• 한국산업정보학회 2002년도 춘계학술대회 논문집
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• pp.166-169
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• 2002

본 논문은 명령형 언어 While의 요약해석을 모델검사기 SMV에서 구현하고 정보흐름 안전성을 검사하는 CTL 논리식을 적용하는 방법을 설명한다. 주어진 While 프로그램의 요약 프로그램을 SMV 프로그램으로 변환하는 방법과 정보흐름 안전성 검사를 위한 CTL 논리식의 유도과정을 보여준다. 요약해석 기를 직접 구현하는 것보다 모델 검사를 이용하는 것이 다양한 안전성 검사를 수행하기에 더욱 적합하다.

• 한국통신학회논문지
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• 제21권4호
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• pp.1059-1067
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• 1996

A 128/129 dual-modulus prescalar IC is designed for application to frequency synthesizers in high frequency communication systems. The FET logic used in this design is SCFL(Source Coupled FET Logic), employing depletion-mode 1.mu.m gate length GaAs MESFETs with the threshold voltage of -1.5V. This circuit consists of 8 flip-flops, 3 OR gates, 2 NOR gates, a modulus control buffer and I/O buffers, which are integrated with about 440 GaAs MESFETs on dimensions of 1.8mm. For $V_{DD}$ and $V_{SS}$ power supply voltages 5V and -3.3V Commonly used in TTL and ECL circuits are determined, respectively. The simulation results taking into account the threshold voltage variation of .+-.0.2V and the power supply variation of .+-.1V demonstrate that the designed prescalar can operate up to 2GHz. This prescalar is fabricated using the ETRI MMIC foundary process and the measured maximum operating frquency is 621MHz.

• 한국초전도ㆍ저온공학회논문지
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• 제8권2호
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• pp.17-19
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• 2006

A novel clock distribution technique for pipelined-RSFQ logics using variable Bias Currents of JTLs as delay-medium is newly proposed. RSFQ logics consist of several logic gates or blocks connected in a pipeline structure. And each block has variable delay difference. In the structure, this clock distribution method generates a set of clock signals for each logic blocks with suitable corresponding delays. These delays, in the order of few to tens of pS, can be adjusted through controlling bias current of JTL of delay medium. While delays with resistor value and JJ size are fixed at fabrication stage, delay through bias current can be controlled externally, and thus, is heavily investigated for its range as well as correct operation within current margin. Possible ways of a standard delay library with modular structure are sought for further modularizing Pipelined-RSFQ applications. Simulations and verifications are done through WRSpice with Hypres 3-um process parameters.

• 전자공학회논문지A
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• 제32A권4호
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• pp.93-102
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• 1995

This paper introduces a general purpose Associative Processor(AP) which is very efficient for search-oriented applications. The proposed architecture consists of three main functional blocks: Content-Addressable Memory(CAM) arry, row logic, and control section. The proposed AP is a Single-Instruction, Multiple-Data(SIMD) device based on a CAM core and an array of high speed processors. As an application for the proposed hardware, we present a parallel algorithm to solve a global routing problem in the layout process utilizing the processing capabilities of a rudimentary logic and the selective matching and writing capability of CAMs, along with basic algorithms such a minimum(maximum) search, less(greater) than search and parallel arithmetic. We have focused on the simultaneous minimization of the desity of the channels and the wire length by sedking a less crowded channel with shorter wire distance. We present an efficient mapping technique of the problem into the CAM structure. Experimental results on difficult examples, on randomly generated data, and on benchmark problems from MCNC are included.

• 상하수도학회지
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• 제31권5호
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• pp.409-414
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• 2017

In this study, we divided the process operation scenarios into three categories based on raw water temperature and turbidity. We will select and operate the process operation scenario according to the characteristics of the raw water. The number of algae in the DAF treated water has been analyzed to be less than 100 cells/mL. These results indicated that the DAF process is effective in removing the algae. In addition, the scenario of the integrated management decision algorithm of the DAF process was developed. DAF pilot plants ($500m^3/day$) process has shown a constantly sound performance for the treatment of raw water, yielding a significantly low level of turbidity (DAF treated water, 0.21~1.56 NTU).

• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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• 제15권4호
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• pp.265-269
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• 2009

정형명세기법은 안전최우선시스템 소프트웨어의 안전성을 일정 수준 이상 보장할 수 있는 기법으로서, 원자력 발전소의 디지털 제어시스템의 개발에 사용되고 있다. 정형명세기법 NUSCR로부터 Programmable Logic Controller(PLC) 시스템을 구현하기 위한 소프트웨어인 Function Block Diagram(FBD) 프로그램을 자동으로 생성하는 기법[1]이 개발되었으나, 이를 지원하는 자동화 도구가 없어 이 기법이 널리 사용되지 못하였다. 본 논문에서는 이어 자동생성 기법을 지원하기 위하여 개발된 자동화 도구 NuSCRtoFBD를 소개한다. 본 연구에서 제안하는 NuSCRtoFBD 도구를 사용하여 NuSCR로부터 FBD를 자동생성 함으로써, 기존의 수동 프로그래밍 작업에서 발생했던 다수의 오류들을 줄일 수 있다.

• Journal of Electrical Engineering and Technology
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• 제4권4호
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• pp.515-520
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• 2009

According to the operating characteristics of pump applications, they should exhibit high efficiency and energy saving capabilities throughout the whole operating process. A novel efficiency optimization control strategy is presented here to meet the high efficiency demand of a variable speed Permanent Magnet Synchronous Motor (PMSM). The core of this strategy is the excellent integration of mended maximum torque to the current control algorithm, based on the losses model during the dynamic and the grade search method with changed step by fuzzy logic during the steady. The performance experiments for the control system of a variable speed high efficiency PMSM have been completed. The test results verified that the system can reliably operate with a different control strategy during dynamic and steady operation, and the system exhibits better performance when using the efficiency-optimization control.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.1114-1115
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• 2007

In this paper, a new speed sensorless control based on a fuzzy compensator are proposed for the interior permanent magnet synchronous motor (IPMSM) drives. The conventional proportional plus integrate(PI) control are very sensitive to step change of the command speed, parameter variations and load disturbance. To cope with these problems of the PI control, the estimated speeds are compensated by using the fuzzy logic controller (FLC). In the FLC used by the speed compensator of the IPMSM, the system control parameters are adjusted by the fuzzy rule based system, which is a logical model of the human behavior for process control. The effectiveness of algorithm is confirmed by the experiments.

• 항공우주시스템공학회지
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• 제13권3호
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• pp.40-47
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• 2019

본 논문은 무인항공기 체계(UAS; unmanned aerial system)의 비행체 탑재장비 및 지상에서 운용하는 장비의 연동 검증을 위한 체계통합실험실(SIL; system integration laboratory) 및 체계통합시험(SIT; system integration test)의 환경 구축 및 이를 통한 검증방법에 대하여 다룬다. SIL 내 구축된 지상통제체계, 데이터링크체계, 비행체 탑재장비, 임무장비(EO/IR, SAR) 등과 같은 부체계간의 인터페이스 환경 및 모의 비행을 통한 체계 운용로직의 검증방법과 실험실 레벨에서의 검증이 완료된 각 부체계를 실제 시험 환경에서 검증하는 방법에 대해 기술한다.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 2001년도 추계학술대회(한국공작기계학회)
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• pp.8-13
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• 2001

In the turning process, the feed is usually selected by a machining operator considering workpiece, cutting tool and depth of cut. Even if this selection can avoid power saturation or tool breakage, it is usually conservative compared to the capacity of the machine tools and can reduce the productivity significantly. This paper proposes a selection method of the feed and the reference cutting force based on MRR(material removal rate), maximum spindle power and specific energy. In order to estimate and control cutting force accurately in transient and steady state, this study utilizes a synthesized cutting force estimation method and a Fuzzy controller. The experimental results present that these systems can be useful for the FMS(flexible manufacturing system) and unmanned automation system.