• Journal of the Korean Institute of Gas
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• v.16 no.6
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• pp.41-47
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• 2012

There are PFD(Process Flow Diagram) and P&ID(Piping and Instrument Diagram) for designing and managing chemical process efficiently. They provide the operation condition and equipment specifications of chemical process, but they do not provide the reliability of chemical process. Therefore, in this study, Reliability Flow Diagram(RFD) which provide the cycle and time of preventive maintenance has been developed using Directed Graph Analysis methodology. Directed Graph Analysis methodology is capable of assessing the reliability of chemical process. It models chemical process into Directed Graph with nodes and arcs and assesses the reliability of normal operation of chemical process by assessing Directed Graph sequential. In this paper, the chemical process reliability transition according to operation time was assessed. And then, Reliability Flow Diagram has been developed by inserting the result into P&ID. Like PFD and P&ID, Reliability Flow Diagram provide valuable and useful information for the design and management of chemical process.

• The KIPS Transactions:PartA
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• v.9A no.2
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• pp.171-180
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• 2002

The effective and accurate data flow problem analysis uses the dominator tree and DJ graphs. The data flow problem solving is to safely reduce the flow graph to the dominator tree. The flow graph replaces a parse tree and used to accurately reduce either reducible or irreducible flow graph to the dominator tree. In this paper, in order to utilize Tarian's path compress algorithm, the Top node finding algorithm is suggested and the existing delay reduction algorithm is improved using Path compression. The delayed reduction a1gorithm using path compression actually compresses the pathway of the dominator tree by hoisting the node while reducing to delay the DJ graph. Realty, the suggested algorithm had hoisted nodes in 22% and had compressed path in 20%. The compressed dominator tree makes it possible to analyze the effective data flow analysis and brings the improved effect for the complexity of code optimization process with the node hoisting effect of code optimization process.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.30 no.3
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• pp.493-501
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• 2020

For the obfuscation of Flow Analysis on the Android operating system, the size of the Flow Graph can be large enough to make analysis difficult. To this end, a library in the form of aar was implemented so that it could be inserted into the application in the form of an external library. The library is designed to have up to five child nodes from the entry point in the dummy code, and for each depth has 2n+1 numbers of methods from 100 to 900 for each node, so it consists of a total of 2,500 entry points. In addition, entry points consist of a total of 150 views in XML, each of which is connected via asynchronous interface. Thus, the process of creating a Inter-procedural Control Flow Graph has a maximum of 14,175E+11 additional cases. As a result of applying this to application, the Inter Procedure Control Flow Analysis too generates an average of 10,931 edges and 3,015 nodes with an average graph size increase of 36.64%. In addition, in the APK analyzing process showed that up to average 76.33MB of overhead, but only 0.88MB of execution overhead in the user's ART environment.

• 전기의세계
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• v.22 no.5
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• pp.12-18
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• 1973

This paper deals with Linear Programming by Signal Flow Graph technique which is different from that of Mason and Coates. The objective function is regarded as variable, and slack variable node, artificial variable node and objective function variable (constant) node are newly defined, which shows the process for optimization of solution very intuitively. Also methods for solving L.P. and examples with subject to Ax.leq.b, Ax=b and Ax.geq.b are presented.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.692-695
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• 2001

The EMFG(Extended Mark Flow Graph) is not only a powerful tool to. designing the discrete-event system conceptually or specifically but also a good representation tool for implementing the system directly. We present a transitions-firing process and automatic changes of the number of marks in each box as a firing determination algorithm with the incident matrix and the state transition equation. The convenient analysis and design of a system as well as Computer Aided Design is possible because the operations of an EMFG ran be represented in the mathematical analysis with ease.

• Journal of Korean Elementary Science Education
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• v.31 no.3
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• pp.386-397
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• 2012

The purpose of this study was to find a way to improve the science textbook graph through analyzing teachers' interpretation process with eye movement tracking when they try to read the science textbook graph. Participants in this project were 10 elementary school teachers while bar graphs, line graphs, pie charts in 2007 revision science textbooks were used as materials. SMI (SensoMotoric Instruments)' iView X TM RED 120 Hz was used in order to collect eye movement data. Although subjects paid attention to the title of the graph at first, the consequence of the eye fixation was changed by the composition of the graph in case of the rest of areas. In particular, the flow of visual attention and fixation time were affected by the form and configuration of the graph. The diversity of graph construction caused confusion in interpreting graphs; the manner of presenting title, the difference of background colors, size of characters, the name of X-axis and Y-axis. Out results showed that the conformation of graphs as well as the presentation of each factor should be composed in accordance with the educational purpose for helping users to easier understanding.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.9 no.6
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• pp.96-102
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• 2000

Spinning mechanism is generally used in coasting process on grass plates. Rebounding PR(Photo Resist) which leads to occur inferiority of coating process is caused by vibrational energy of whole coating system. In this study, the sensitivity analysis is performed to analyze and reduce vibrational terms in the spin coating system. The sensitivity analysis is bared on the numerical expression of this system. By the bond graph method. power flow of each system is represented by some basic bond graph elements. Any energy domain system is modeled using the unified elements. The modelled spin coater system is verified with power spectrum data measured by FFT analyzer. As the results of verifying model parameters and sensitivity analysis, principal factors causing vibration phenomenon are mentioned. A study on vibration method in the spin coating system is discussed.

• The KIPS Transactions:PartD
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• v.15D no.2
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• pp.197-206
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• 2008

The CTOC framework was implemented to efficiently perform analysis and optimization of the Java bytecode that is often being used lately. In order to analyze and optimize the bytecode from the CTOC, the eCFG was first generated. Due to the bytecode characteristics of difficult analysis, the existing bytecode was expanded to be suitable for control flow analysis, and the control flow graph was drawn. We called eCFG(extended Control Flow Graph). Furthermore, the eCFG was converted into the SSA Form for a static analysis. Many loops were found in the conversion program. The previous CTOC performed conversion directly into the SSA Form without processing the loops. However, processing the loops prior to the SSA Form conversion allows more efficient generation of the SSA Form. This paper examines the process of finding the loops prior to converting the eCFG into the SSA Form in order to efficiently process the loops, and exhibits the procedures for generating the loop tree.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1013-1016
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• 1998

A method for generation of design verification tests from behavior-level VHDL program is presented. Behavioral VHDL programs contain multiple communicating processes, signal assignment statements. So for large, complex system, it is difficult problem to test or simulation. In this paper, we proposed a new hardware design verification method. For this method generates control flow graph(CFG.) and process modeling graph(PMG) in the given under the testing VHDL program. And this method proved very effective that all the assumed design errors could be detected.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.228-234
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• 2006

This paper describes a systematic process which can generate a complete circuit specification efficiently for a given recursive DSP algorithm based on an optimal multiprocessor scheduler. The process is composed of two states: scheduling and circuit synthesis. The scheduling part accepts a fully specified flow graph(FSFG) as an input, and generates an optimal synchronous multiprocessor schedule. Then the circuit synthesis part translates the modified schedule into a complete circuit diagram including a control specification. The circuit diagram can be applied to a silicon compiler for VLSI layout generation. This paper illustrates the whole process with an example of a second order Gray-Market lattice filter.