• Journal of the Korean Institute of Telematics and Electronics
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• v.4 no.4
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• pp.19-21
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• 1967

A technique is illustrated for the selection of basis rows from a cyclic prime implicant table. This technique is more systematic and effective than a trial and process, and the results of this technique agree well with the ones solved by Gimpel's Luccio's reduction technique.

• Journal of the Korea Society of Computer and Information
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• v.19 no.3
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• pp.109-117
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• 2014

This paper revises the Quine-McCluskey Algorithm to circuit minimization problems. Quine-McCluskey method repeatedly finds the prime implicant and employs additional procedures such as trial-and-error, branch-and-bound, and Petrick's method as a means of circuit minimization. The proposed algorithm, on the contrary, produces an implicant chart beforehand to simplify the search for the prime implicant. In addition, it determines a set cover to streamline the search for $1^{st}$ and $2^{nd}$ essential prime implicants. When applied to 3-variable and 4-variable experimental data, the proposed algorithm has indeed proved to obtain the optimal solutions much more simply and accurately than the Quine-McCluskey method.

• Journal of the Korea Society of Computer and Information
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• v.20 no.4
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• pp.95-102
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• 2015

This paper proposes a simple algorithm for circuit minimization. There are currently two effective heuristics for circuit minimization, namely manual Karnaugh maps and computable Quine-McCluskey algorithm. The latter, however, has a major defect: the runtime and memory required grow $3^n/n$ times for every increase in the number of variables n. The proposed algorithm, however, extracts the prime implicants (PI) that cover minterms of a given Boolean function by deriving an implicants table based on frequency. From a set of the extracted prime implicants, the algorithm then eliminates redundant PIs again based on frequency. The proposed algorithm is therefore capable of minimizing circuits polynomial time when faced with an increase in n. When applied to various 3-variable and 4-variable cases, it has proved to swiftly and accurately obtain the optimal solutions.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.39 no.12
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• pp.1288-1295
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• 1990

In this paper, we propose a parallel processing model for the efficient selection of Prime Implicants of Logic Functions. This model consists of simple parallel processing nodes, connections between them, Max Net (a part of Hamming Net) and quasi essential Prime Implicant selection standard in simplified cost form. Through these, this model selects essential Prime Implicants in a certain period of time regardless of the number of given Prime Implicants and minterms and also selects quasi essential Prime Implicants in short time.

• 전기의세계
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• v.28 no.12
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• pp.33-40
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• 1979

This mininzation of the multi-output switching function becomes a difficult task when the input varibles and the number of functions increase. This paper describes the optimal selection of prime inplicats for the multi-output switching function by using the Inter-section Table. This procedure is applicable to both manual and computhe programmed realization without complesith. The algorithm is implemented by a computer program in the standard FORTRAN iv language.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.525-528
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• 1988

In this paper, a new multi-output logic minimization algorithm is presented. A base minterm is selected in the given function and the prime implicant is obtained by expanding it in the order of the expansion set that is decided by heuristic method. Input-oriented expansion procedure is used to reduce fan-in and fan-out number. To show the effectiveness of this algorithm, comparative run time with other minimization algorithm is given.

• Journal of the Korean Institute of Telematics and Electronics
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• v.4 no.3
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• pp.2-8
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• 1967

A method is illustrated for minimizing the number of internal states in incompletely specified sequential networks. The starting point for minimizing technique in this paper is the set of maximal compatibility classes which covers the original flow table and the minimal covering can be obtained directly by employing three rules. The reduction techniques for prime implicant table or covering and closure table are not employed in this paper. Although the minimizing technique is applied to some specific problems, it is believed that the concepts are general in nature and can be applied to any type of incompletely specified flow tables.

• Journal of the Korea Society of Computer and Information
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• v.17 no.6
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• pp.83-92
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• 2012

This paper suggests an improved method of grouping minterms based on the Decimal-Valued Matrix (DVM) method. The DVM is a novel approach to Boolean logic minimization method which was recently developed by this author. Using the minterm-based matrix layout, the method captures binary number based minterm differences in decimal number form. As a result, combinable minterms can be visually identified. Furthermore, they can be systematically processed in finding a minimized Boolean expression. Although this new matrix based approach is visual-based, the suggested method in symmetric grouping cell values can become rather messy in some cases. To alleviate this problem, the enhanced DVM method that is based on multi-level groupings of combinable minterms is presented in this paper. Overall, since the method described here provides a concise visualization of minterm groupings, it facilitates a user with more options to explore different combinable minterm groups for a given Boolean logic minimization problem.