• Journal of Power Electronics
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• 제16권3호
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• pp.840-848
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• 2016

A primary-side regulation AC-DC converter operating in the PFM (Pulse Frequency Modulation) mode with a high precision output current is designed, which applies a novel inductance compensation technique to improve the precision of the output current, which reduces the bad impact of the large tolerance of the transformer primary side inductance in the same batch. In this paper, the output current is regulated by the OSC charging current, which is controlled by a CC (constant current) controller. Meanwhile, for different primary inductors, the inductance compensation module adjusts the OSC charging current finely to improve the accuracy of the output current. The operation principle and design of the CC controller and the inductance compensation module are analyzed and illustrated herein. The control chip is implemented based on a TSMC 0.35μm 5V/40V BCD process, and a 12V/1.1A prototype has been built to verify the proposed control method. The deviation of the output current is within ±3% and the variation of the output current is less than 1% when the inductances of the primary windings vary by 10%.

• Nuclear Engineering and Technology
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• 제54권9호
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• pp.3293-3298
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• 2022

Removing radioactive contaminated metal materials is a vital task during the decommissioning of nuclear power plants to reduce the cost of the post-dismantling process. The laser decontamination technique has been recognized as a key tool for a successful dismantling process as it enables a remote operation in radioactive facilities. It also minimizes exposure of workers to hazardous materials and reduces secondary waste, increasing the environmental friendless of the post-dismantling processing. In this work, we present a thorough and efficient laser decontamination approach using a single-mode continuous-wave (CW) laser. We subjected stainless steels to a surface-removal process that repetitively exposes the laser to a confined region of ~75 ㎛ at a high scanning rate of 10 m/s. We evaluate the decontamination performance by measuring the removal depth with a 3D scanning microscope and further investigate optimal removal conditions given practical parameters such as the laser power and scan properties. We successfully removed the metal surface to a depth of more than 40 ㎛ with laser power of 300 W and ten scans, showing the potential to achieve an extremely high DF more than 1000 by simply increasing the number of scans and the laser power for the decontamination of primary circuits.

• 한국정보통신학회논문지
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• 제3권1호
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• pp.235-244
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• 1999

본 논문에서는 새로운 동적 컴팩션(dynamic compaction) 알고리즘을 제안하고 이용하여 CMOS 디지털 회로의 IDDQ 테스트패턴 생성한다. 제안된 알고리즘은 프리미티브 게이트 내부에서 발생하는 GOS, 브리징 고장을 검출할 수 있는 프리미티브 고장패턴을 이용하여 초기 테스트패턴을 구하고, 초기 테스트패턴에 있을 수 있는 don't care(X)의 수를 줄여 테스트 패턴의 수를 감소시킨다. 그리고 난수와 4 가지 제어도(controllability)를 사용하여 백트레이스를 수행시키는 방법을 제안한다. ISCAS-85 벤치마크 회로를 사용하여 모의 실험한 결과 큰 회로에서 기존의 정적 컴팩션 알고리즘에 비하여 45% 이상 테스트패턴 수가 감소함을 확인하였다.

• The Korean Journal of Physiology and Pharmacology
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• 제26권2호
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• pp.69-75
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• 2022

Chronic pain is induced by tissue or nerve damage and is accompanied by pain hypersensitivity (i.e., allodynia and hyperalgesia). Previous studies using in vivo two-photon microscopy have shown functional and structural changes in the primary somatosensory (S1) cortex at the cellular and synaptic levels in inflammatory and neuropathic chronic pain. Furthermore, alterations in local cortical circuits were revealed during the development of chronic pain. In this review, we summarize recent findings regarding functional and structural plastic changes of the S1 cortex and alteration of the S1 inhibitory network in chronic pain. Finally, we discuss potential neuromodulators driving modified cortical circuits and suggest further studies to understand the cortical mechanisms that induce pain hypersensitivity.

• 센서학회지
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• 제23권2호
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• pp.73-81
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• 2014

Silicon PIN diode radiation sensors and CMOS readout circuits were designed and fabricated in this study. The PIN diodes were fabricated using a 380-${\mu}m$-thick 4-inch n+ Si (111) wafer containing a $2-k{\Omega}{\cdot}cm$ n- thin epitaxial layer. CMOS readout circuits employed the driving and signal processes in a radiation sensor were mixed with digital logic and analog input circuits. The primary functions of readout circuits are amplification of sensor signals and the generation of the alarm signals when radiation events occur. The radiation sensors and CMOS readout circuits were fabricated in the Institute of Semiconductor Fusion Technology (ISFT) semiconductor fabrication facilities located in Kyungpook National University. The performance of the readout circuit combined with the Si PIN diode sensor was demonstrated.

• 전자공학회논문지A
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• 제31A권2호
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• pp.94-103
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• 1994

In testing for practical scan disigned logic circuits, there may exist logic value constraints on some part of primary inputs due to various requirements on design and test. This paper presents a logic value system called taboo logic values which targets the test pattern generation of logic circuits under logic value constraints. The taboo logic system represents the logic value constraints and identifies additional logic value constraints through the implication of the tqaboo logic values using a taboo logic calculus. Those identified logic value constraints will guide the search during the test pattern generation of avoid the unfruitful searches and to identify redundant faults due to the logic value constraints very quickly. Finally, experimental results on ISCAS85 benchmark circuits will demonstrate the efficiency of the taboo logic values.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.9-12
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• 2008

Mathematical singularities of circuit equations with three-phase ideal transformer connections are studied. Three-wired wye-wye connections, delta-delta connections, and primary four-wired wye-delta connections are singular. The matrices of their circuit equations have zeros in their eigenvalues. Three-wired wye-delta connections, wye-wye-delta connections, and primary four-wired wye-wye connections are not singular. The physical meaning of their singularities is that they are sensitive and prone to be ill-conditioned. Equivalent shunt admittances representing ion losses and magnetizing inductances make the singular matrices non-singular in wye-connected circuits. And, equivalent series impedances representing copper losses and leakage inductances make the singular matrices non-singular in delta-connected circuits. The tableau analysis is used for the study.

• 대한전자공학회논문지
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• 제11권4호
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• pp.17-22
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• 1974

본논문에서는 조합논리회로의 결함검출에 관한 문제를 취급하였는데 먼저 fan-out가 없는 회로에 대한 결함검출방법을 논하고 이 방법을 fan-out가 있는 회로에 확장하였다. Fan-out가 있는 회로에서는 내부 fan-out점을 전후하여 fan-out가 없는 부분회로로 분리구분하고 우선 각 부분회로에 대한 최소테스트집합을 구한다. 다음에 각 부분테스트집합사이에서 최대한으로 병립가능한 테스트를 조합하여 전체회로에 대한 종합적인 입력테스트벡터를 구한다. 이와같은 절차에 의하면 테스트수가 최소인 완전테스트집합이 용이하게 구해질 뿐만 아니라 검출가능한 결함 및 불가능한 결함이 명확하게 판가름 된다.

• 한국정보과학회논문지:시스템및이론
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• 제30권9호
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• pp.504-511
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• 2003

논리회로 합성에서 함수의 대칭성을 이용하여 면적이나 시간 지연을 최소화하는 문제는 많은 시간동안 연구되어 왔다. 본 논문은 최근 들어 면적이나 시간지연 보다도 더 중요하게 여겨지는 전력 소모를 최소화하는데, 회로 대칭성이 어떻게 이용되는 지에 대한 연구를 소개한다. 이 논문에서 회로의 대칭성에 대한 폭넓은 정의를 소개하고, 각 대칭성간의 관계에 대해 논의하며, 각 회로의 대칭성이 어떻게 전력을 줄이는데 유용할 수 있는지에 대해 논의한다. 또한, 회로에 존재하는 주 입력(primary input)과 내부 노드사이에 존재하는 대칭성을 찾아내는 알고리즘을 소개한다. 이 논문에서 소개하는 알고리즘의 특징은 첫째, 면적이나 속도지연의 증가가 거의 없이, 전력 소모를 줄여주는 효과적인 재합성 기법이란 것이다. 둘째, 대부분의 다른 휴리스틱(heuristic) 알고리즘과는 달리, 회로의 스위칭 (switching) 양에 있어 단조 향상(monotonic improvement)을 보장한다. 이미 잘 알려진 바와 같이 CMOS 회로에서는 스위칭 양이 전력소모에 대부분을 차지하므로, 알고리즘의 적용 후에 회로가 전력 소모 면에서 계속적인 향상을 이룰 수 있게 한다는 점에서 매우 효과적이라 하겠다. 알고리즘의 효과를 검증하기 위해서, MCNC 벤치마크 회로를 이용하여 실험을 시행하였고, 실험 결과, 속도나 면적에 대한 오버헤드가 거의 없으면서 평균 12%의 전력 소모를 줄일 수 있었다.

• 전자공학회논문지B
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• 제31B권6호
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• pp.63-70
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• 1994

In this paper, we propose a fault simulation method based on primary output in combinational circuit. In the deterministic test pattern generation, each test pattern is genterated incrementally. The test pattern is applied to the primary inputs of circuit under test to simulate faults. We detect the faults with respect to each primary output. The fault detection with resptect to each primary output is reflected by the corresponding bit in the detection words, and efficient fault detection for the reconvergent fan-out stem is achieved with dynamic fault propagation. As an experimental result of the fault simulation with our method for the several bench mark circuits, we illustrated the good performance showing that the number of gates to be activated is much reduced as compared with other method which is not based on primary output.