• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.279-282
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• 1999

Frequency divider selects the channel of the frequency synthesizer. General programmable divider has many flip-flops to realize all integer division value and stability problem by using dual modules prescaler. In this paper, a new architecture of programmable divider is proposed and designed to improve these problems. The proposed programmable divider has only thirteen flip-flops. The programmable divider is designed by 0.65${\mu}{\textrm}{m}$ CMOS technology and HSPICE. Operating frequency of the programmable divider is 200MHz with a 3V supply voltage.

• Journal of IKEEE
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• v.11 no.1 s.20
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• pp.15-23
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• 2007

This paper describes a dual frequency synthesizer designed in a 0.2$\mu$m CMOS technology for wireless LAN applications. The design is focused mainly on low-power characteristics. Power dissipation is minimized especially in VCO and prescaler design. The designed synthesizer includes all building blocks for elimination of external components, other than the crystal. Its operating frequency can be programmed by external data. It operates in the frequency range of 2.3GHz to 2.7GHz (RF) and 250MHz to 800MHz (IF) and consumes 5.14mA at 2.5GHz and 1.08mA at 0.5GHz from a 2.5V supply. The measured phase noise is -85dBc/Hz in-band and -105dBc/Hz at 1MHz offset at IF band. The die area is 1.7mm$\times$1.7mm.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.435-436
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• 2008

This paper presents a dual band frequency synthesizer for GSM and Wideband CDMA which is designed in a standard 0.13um CMOS 1P6M process. The shared components include phase frequency detector (PFD), charge pump (CP), loop filter, integer frequency divider(128/129 DMP, 4bit PC, 3bit SC) and Low noise Ring-VCO. A high-speed low power dual modulus prescaler is proposed to operate up to 2.1GHz at 3.3V supply voltage with 2mW power consumption by simulation. The simulated phase noise of VCO is -101dBc/Hz at 200kHz offset frequency from 1.9GHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.1
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• pp.41-48
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• 2002

This paper presents a 18-mW, 2.5-㎓ fractional-N frequency synthesizer with l-bit $4^{th}$-order interpolative delta-sigma ($\Delta{\;}$\sum$)modulator to suppress fractional spurious tones while reducing in-band phase noise. A fractional-N frequency synthesizer with a quadruple prescaler has been designed and implemented in a $0.5-\mu\textrm{m}$ 15-GHz $f_t$ BiCMOS. Synthesizing 2.1 GHzwith less than 200 Hz resolution, it exhibits an in-band phase noise of less than -85 dBc/Hz at 1 KHz offset frequency with a reference spur of -85 dBc and no fractional spurs. The synthesizer also shows phase noise of -139 dBc/Hz at an offset frequency of 1.2 MHz from a 2.1GHz center frequency.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.671-672
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• 2006

Recently Communication with using IrDA is bing used in various fields. In this paper I designed a receiver by fabricating hardware that used to be fabricated through software, so anyone who don't have knowledge on IrDA can receive Ir Signal easily. This receiver can communicate with CPU through 8 bit data and 3 bit address. Also this receiver can use user-needed CLK because this receiver embodied 16 bit CLK Prescaler.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.890-893
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• 2003

In this paper, we have designed the fractional-N frequency synthesizer for bluetooth system using 0.35-um CMOS technology and 3.3-V single power supply. The designed synthesizer consist of phase-frequency detector (PFD), charge pump, loop filter, voltage controlled oscillator (VCO), frequency divider, and sigma-delta modulator. A dead zone free PFD is used and a modified charge pump having active cascode transistors is used. A Multi-modulus prescaler having CML D flip-flop is used and VCO having a tuning range from 746 MHz to 2.632 GHz at 3.3 V power supply is used. Total power dissipation is 32 mW and phase noise is -118 dBc/Hz at 1 MHz offset.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.7 s.337
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• pp.35-40
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• 2005

This paper proposes a fractional-N phase-locked loop (PLL) frequency synthesizer using the 3rd order ${\Delta}{\sum}$ modulator for 900MHz medium speed wireless link. The LC voltage-controlled oscillator (VCO) is used for the good phase noise property. To reduce the lock-in time, a charge pump has been developed to control the pumping current according to the frequency steps and the reference frequency is increased up to 3MHz. A 36/37 fractional-N divider is used to increase the reference frequency of the phase frequency detector (PFD) and to reduce the minimum frequency step simultaneously. A 3rd order ${\Delta}{\sum}$ modulator has been developed to reduce the fractional spur VCO, Divider by 8 Prescaler, PFD and Charge pump have been developed with 0.25um CMOS, and the fractional-N divider and the third order ${\Delta}{\sum}$ modulator have been designed with the VHDL code, and they are implemented through the FPGA board of the Xilinx Spartan2E. The measured results show that the output power of the PLL is about -lldBm and the phase noise is -77.75dBc/Hz at 100kHz offset frequency. The minimum frequency step and the maximum lock-in time are 10kHz and around 800us for the maximum frequency change of 10MHz, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.8
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• pp.1297-1304
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• 2002

The phase locked oscillator having a low phase noise and high output in Ku-band was designed. To obtain the low phase noise and high output characteristics of oscillator, the nonlinear equivalent circuits of p-HEMT was analyzed by TOM method and we have decided the trade-off bias point between the low phase noise and the output power of oscillator. The designed phase locked oscillator with prescaler for stable operation, experiment results exhibits output power of 1003m with phase noise in the phase locked state of -824BC/HB at 10mz offset from 13.250Hz, and simulation result of 1003m output power in the phase noise -840Bc/Hz at 10KHz offset frequency respectively. a good agreement has been obtained between simulations and experiments results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3215-3226
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• 1996

In this paper a K-band harmonic oscillator competitive to ordinary Push-Push type oscillators is introduced. This oscillator is composed of two-X-band dielectric resonance circuits. To favor its harmonic generation, the load effect and the bias effect are studied to allow the maximum harmonic distortion. As results, the dielectric resonated load and the class A bias are used for the 2nd harmonic generation. analytical study for modelling of voltage controlled dielectric resonator is carried out with theoretical background. The performance of the circuit is evaluated by simulation using harmonic balanced method. The novel structure has ont only a voltage tuning circuit but also an output port at fundamental frequency as the function of prescaler for phase lockede loop application on the just single oscillation structure. In experimentation, the output freqneyc of the 2nd harmonic signal is 20.5GHz and the maximum power level of output is +5.5dBm without additional post amplifiers. the harmonic oscillator exhibits -30dBc of high fundamental frequency rejection without added extra filters. The phase noise of -90dBc/Hz at 100kHz off-carrier has been achieved under free running condition, that satisfies phase noise requirement of IESS 308. The proposed oscillator may be utilized as the clean and stable fixed local oscillator in Transmit Block Upconvertor(TBU) or Low oise Block downconvertor(LNB) for K/Ka-band digital communications and satellite broadcastings.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1312-1315
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• 2002

This research describes the design of a fully integrated fractional-N frequency synthesizer intended for the local oscillator in IMT-2000 system using 0.18-$\mu\textrm{m}$ CMOS technology and 1.8-V single power supply. The designed fractional-N synthesizer contains following components. Modified charge pump uses active cascode transistors to achieve the high output impedance. A multi-modulus prescaler has modified ECL-like D flip-flop with additional diode-connected transistors for short transient time and high frequency operation. And phase-frequency detector, integrated passive loop filter, LC-tuned VCO having a tuning range from 1.584 to 2.4 ㎓ at 1.8-V power supply, and higher-order sigma-delta modulator are contained. Finally, designed frequency synthesizer provides 5 ㎒ channel spacing with -122.6 dBc/Hz at 1 ㎒ in the WCDMA band and total output power is 28 mW.