• 전자공학회논문지B
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• 제31B권1호
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• pp.49-56
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• 1994

This paper describes the design principles and methods of electronic processor for thermal imager with the SPRITE detector, operating in the 8-12 micron band. The thermal imager consists of a optical scanner containing the detector and an electrical signal processor. The optical scanner utilizing rotating polygon and oscillating mirror, is 2-dimensional serial/parallel scan type using 5 elements of the detector. And the electronic processor has pre-processing of 5 chnanel's thermal signal from the detector, and performs digital scan conversion to reform the parallel data stream into serial analog data compatible with conventional RS-170 video. Through the designed electronic processor, we have acquired a satisfactory thermal image. And the MRTD (Minimum Resolvable Temperature Difference) is 0.5$^{\circ}$K at 7.5 cycles/mm.

• 전산구조공학
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• 제22권5호
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• pp.44-51
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• 2009

• 한국산학기술학회논문지
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• 제16권10호
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• pp.6673-6678
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• 2015

최근 빈번히 건설되고 있는 비정형 건축물들은, 개별부재의 수직/수평적 연결방식 에서 벗어나, 외관 및 내부 구성요소들의 단면이 자유롭게 변화되는 곡선의 형태를 띠고 있다. 이러한 구조물의 안정성 평가를 위해서 고전적 방식의 유한요소 해석기법이 적용된 상용프로그램이 사용되고 있으나, 과도한 절점분할 방식 또는 유한요소망(Finite Element Mesh)의 도입으로 인하여 해석시간이 길어지고 사용성 및 해석 정밀도가 낮은 문제점을 안고 있다. 따라서 본 연구에서는, 전술된 문제점을 개선하기 위하여, 임의의 곡률을 가진 단위 부재 및 단위요소에 대한 수학적 해석모형을 활용하여 비정형구조물에 대한 구조안정성 평가를 효과적으로 수행할 수 있는 전후처리 모듈을 개발하였다. 본 연구에서 개발된 전후처리 모듈은 곡선형 부재의 곡률을 NURBS 제어점을 이용하여 제어할 수 있도록 개발되었으며, 그로 인해 상용프로그램보다 빠른 형상 모델링이 가능하였다. 또한, 자유로운 형상에 대한 시각적 확인이 가능하여 비정형 건축물의 형상과 거동양상의 현실적인 묘사가 가능하였다.

• 전자공학회논문지S
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• 제35S권1호
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• pp.105-113
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• 1998

A new image processor is implemented for high-speed digital copiers and facsimiles. The imgage processor performs CCD and CIS interface, pre-processing, enlargement andreduction of gray level image, and various halftoning algorithms. Implemented halftoning algorithms are simple thresholding, fuzzy based mixed mode thresholding, dithering, and edge enhanced error diffusion. The result of binarization is transferred to a printer with serial or paralel output ports. Line by line pipelined data prodessing architecture is employed with time sharing access of the external memory. In receiving mode, it converts the resolution of received binary image for compatibility with conventional facsimile. In copy mode, a line of A3 paper with 400 dpi is processed with in 2.5 ms. The prototype of image processor was implemented usig Laser Programmable Gate Array (LPGA) with 0.8.mu.m technology.

• 한국연소학회:학술대회논문집
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• 한국연소학회 2012년도 제44회 KOSCO SYMPOSIUM 초록집
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• pp.217-219
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• 2012

This study describes 3D RANS simulation of a 2.1 MW swirling pulverized coal flame in a semi-industrial scale furnace. The simulation of pulverized coal combustion involves various models for complex physical processes and needs information of pyrolysis rate, the yields and compositions of volatiles and char especially in coal conversion. The coal conversion information can be acquired by the experiment or the pre-processor code. The empirical model based on the experiment of the IFRF and the structural model based on the pre-processor code of the PC-COAL-LAB were evaluated against the measurement data.

• 산업공학
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• 제10권3호
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• pp.145-153
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• 1997

This paper deals with constructing a scheduling system for a mold manufacturing factory. The scheduling system is composed of 4 submodules such as pre-processor, neural network training, neural networks and simulation. Pre-processor analyzes the condition of workshop and generates input data to neural networks. Network training module is performed by using the condition of workshop, performance measures, and dispatching rules. Neural networks module presents the most optimized dispatching rule, based on previous training data according to the current condition of workshop. Simulation module predicts the earliest completion date of a mold by forward scheduling with the presented dispatching rules, and suggests a possible issue date of a material by backward tracking. The system developed shows a great potential when applied in real mold factory for automotive parts.

• 한국군사과학기술학회지
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• 제20권4호
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• pp.482-490
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• 2017

The radar signal processing procedure is divided into the pre-processing such as frequency down converting, down sampling, pulse compression, and etc, and the post-processing such as doppler filtering, extracting target information, detecting, tracking, and etc. The former is generally designed using FPGA because the procedure is relatively simple even though there are large amounts of ADC data to organize very quickly. On the other hand, in general, the latter is parallel processed by multiple DSPs because of complexity, flexibility and real-time processing. This paper presents the radar signal processor design using FPGA which includes not only the pre-processing but also the post-processing such as doppler filtering, bore-sight error, NCI(Non-Coherent Integration), CFAR(Constant False Alarm Rate) and etc.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.533-536
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• 2006

VIATRON TECHNOLOGIES has developed Field-Enhanced Rapid Thermal Processor (FERTP) system that enables LTPS LCD and AMOLED manufacturers to produce poly-Si films at low cost, high throughput, and high yield. The FE-RTP allows the diverse process options including crystallization, thermal oxidation of gate oxides and fast pre-compactions. The process and equipment compatibility with a-Si TFT lines is able to provide a viable solution to produce poly-Si TFTs using a-Si TFT lines.

• 한국대기환경학회:학술대회논문집
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• 한국대기환경학회 2004년도 추계학술대회 논문집
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• pp.135-136
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• 2004

• 한국통신학회논문지
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• 제34권8C호
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• pp.822-829
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• 2009

본 논문은 선형예측 전처리기을 이용하여 저 전송률 환경에 적합한 HE-AAC의 구조를 제안한다. 저 전송률 환경에서는 HE-AAC의 적절하지 못한 비트 할당 알고리즘 때문에 많은 스펙트럴 홀(스펙트럼 홀)들이 발생을 하고 있으며, 그로 인해서 심각한 음질의 열화가 발생하고 있다. 이를 해결하기 위해서 선형예측 전처리기을 사용하여 저 전송률에서 비트가 적절하게 할당되도록 하였다. HE-AAC로 들어오는 입력신호는 선형예측 전처리기에 의해서 LP 계수와 레지듀얼 신호로 나눠지게 되며, AAC 부분은 분리된 레지듀얼 신호를 부호화하게 된다. 제안된 방법의 성능 평가를 위해서 지각적 잡음(Perceptual noise)의 측정을 통한 객관적인 실험과 MUSHRA 테스트를 통한 주관적인 실험을 하였고, 그 결과 저 전송률 환경에서 제안된 방법을 사용함으로써 성능을 향상시킬 수 있음을 확인하였다.