• The Transactions of the Korean Institute of Power Electronics
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• v.7 no.1
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• pp.91-100
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• 2002

This paper deals with the ripple reduction of the electromagnetic torque developed in IPMSM(Interior Permanent Magnet Synchronous Motor). Generally, torque ripple is an important causes of vibration and noise of motor. For reducing torque ripple in IPM with nonsinusoidal EMF, the optimal current which is able to control maximum torque/ampere is considered to be introduced In the proposed method. The fact of torque ripple being reduced when the optimal current Is used in motor is verified through simulation and experiment.

• Proceedings of the KIEE Conference
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• 2003.11a
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• pp.220-223
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• 2003

This paper presents VSCOPF(Votage Stability Constrained Optimal Power Flow) algorithm based on SLP(Successive Linear Programming) to interpret the large scale system. Voltage stability index used to this paper is L index to be presented by function form. The objective function consists of load shedding cost minimization. Voltage stability indicator constraint was incorporated in traditional OPF formulation. as well as the objective function and constraints are linearlized and the optimal problem is performed by SLP(Successive Linear Programming). In this paper, the effect of voltage stability limit constraint is showed in the optimal load curtailment problems. As a result, an optimal solution is calculated to minimize load shedding cost guaranteeing voltage security level. Numerical examples using IEEE 39-bus system is also presented to illustrate the capabilities of the proposed formulation.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.535-537
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• 2004

최근의 멀티미디어 시스템 설계 (예: 휴대폰, PDA) 경향에서 전력 소모를 줄이는 연구가 매우 긴요한 상황에, 본 연구는 누설 전류(leakage power)를 줄이는 연산 회로 아키텍쳐 합성 기법을 제안한다. 누설 전류를 줄이기 위한 방법으로 본 연구는 Dual threshold Voltage (Dual-V$_{T}$) 기법을 적용한다. 기존의 연구에서는 회로 설계 단계 중 논리나 트랜지스터 수준에서DUal-V$_{T}$를 적용한 방법과는 달리, 보다 상위 단계인 회로의 아키텍쳐 합성 단계에서의 지연시간 제약 조건을 만족하는 범위에서 최소의 누설전류 소모를 위한 합성 기법을 제안한다 따라서, 지연 시간과 누설전류 간의 Trade-Off를 이용하여 설계 조건에 맞는 융통성 있는 설계 결과를 얻을 수 있는 장점을 제공한다. 본 연구는 케리-세이브 가산기 (Carry-Save Adder) 모듈의 생성 과정에 국한된 합성 알고리즘의 적용을 보이고 있지만, 일반적인 연산 모듈을 사용한 아키텍쳐 설계 과정에서도 본 알고리즘을 쉽게 변형, 적용할 수 있다.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.87-88
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• 2014

조명용 LED의 보급확산에 따라 LED 구동용 전원장치에 대한 수요가 급증하고 있는데, 심각한 문제 중의 하나는 전원장치의 수명이 LED 수명에 비해 매우 짧다는 것이다. 이 문제를 해결하기 위해 전원장치에 포함되어 있는 전해커패시터를 없애야 한다. 또 다른 문제는 전원장치의 60Hz의 교류전원을 정류하여 회로를 구성해야 하는 특성상 120Hz 리플성분 때문에 플리커가 발생할 수 있다. 따라서 본 연구에서는 전해커패시터를 없앤 조명용 LED 전원장치를 제안하고 120Hz 리플성분에 의한 플리커를 최소화하기 위한 방안도 제시하고자 한다.

• Proceedings of the KSR Conference
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• 2009.05b
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• pp.585-592
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• 2009

The performance of screw compressor depends on lots of design parameters of rotor profile, such as length of seal line, wrap angle, blow hole, suction and discharge port size, number of rotor lobe, etc. The optimum rotor profile makes it possible to increase the compression efficiency with low energy consumption, and to minimize the loss of power. In this research, a new rotor profile design and performance analysis are done by computer simulation. It is expected that the volumetric efficiency is improved because the internal leakage is reduced due to the minimization of blow hole and clearance, and the stiffness of rotors is increased due to the reduction of length to diameter ratio. Also, the specific power consumption will be secured for use ranging from low to high operation speed.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.151-153
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• 2020

PFC( Power Factor Corrector)회로의 목적은 입력전류의 역률 개선을 목적으로 널리 사용되고 있다. 그리고 입/출력 파워의 균형을 위해 대용량의 출력Cap이 사용되며 주로 전해액이 포함된 부품을 사용한다. 그러나 사용 되는 전해Cap은 AC-DC 변환회로의 수명시간을 결정지으며 이를 사용하는 전자제품의 전체 수명을 반영하게 된다. 본 연구는 출력Cap용량을 최소와시키며 이를 대체 할 수 있는 Film Cap을 사용하여 제품의 전체 수명시간을 개선시키는데 목적이 있으며 다이나믹 특성의 부하와 서지성 낙뢰 및 과전압 대책에 대한 해결방안을 실제 시스템에서 구현하고자 한다. 또한 입력 서지 및 다이나믹 부하에 대한 개선 회로를 확인하고 이론적 결과는 200W LED TV에서 검증한다.

• Journal of Communications and Networks
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• v.16 no.1
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• pp.36-44
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• 2014

Exploiting the energy-delay tradeoff for energy saving is critical for developing green wireless communication systems. In this paper, we investigate the delay-constrained energy-efficient packet transmission. We aim to minimize the energy consumption of multiple randomly arrived packets in an additive white Gaussian noise channel subject to individual packet delay constraints, by taking into account the practical on-off circuit power consumption at the transmitter. First, we consider the offline case, by assuming that the full packet arrival information is known a priori at the transmitter, and formulate the energy minimization problem as a non-convex optimization problem. By exploiting the specific problem structure, we propose an efficient scheduling algorithm to obtain the globally optimal solution. It is shown that the optimal solution consists of two types of scheduling intervals, namely "selected-off" and "always-on" intervals, which correspond to bits-per-joule energy efficiency maximization and "lazy scheduling" rate allocation, respectively. Next, we consider the practical online case where only causal packet arrival information is available. Inspired by the optimal offline solution, we propose a new online scheme. It is shown by simulations that the proposed online scheme has a comparable performance with the optimal offline one and outperforms the design without considering on-off circuit power as well as the other heuristically designed online schemes.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.27 no.12
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• pp.1772-1780
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• 2003

An optimal soot blowing system has been developed for an optimal operation of power utility boilers by both minimization of the use of steam and the number of soot blowers worked during soot blowing. Traditionally, the soot blowing system has been operated manually by operators. However, it causes the reduction of power and thermal performance degradation because all soot blowers installed in the plant should be worked simultaneously even there are lots of tubes those are not contaminated by slagging or fouling. Heat transfer area is divided into four groups, furnace, convection area including superheater, reheater and economizer, and air preheater in the present study. The condition of cleanness of the tubes is calculated by several parameters obtained by sensors. Then, a part of soot blowers works automatically where boiler tubes are contaminated. This system has been applied in a practical power plant. Therefore, comparison has been done between this system and manual operation and the results are discussed.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.2
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• pp.227-233
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• 2000

In this paper, we present a new high-level data path synthesis algorithm which solves the two design problems, namely, scheduling and allocation, with power minimization as a key design parameter. From the observations in previous works on data path synthesis for low power, we derive an integer programming (IP) formulation for the problem, from which we then develop an efficient heuristic to carry out the scheduling and allocation simultaneously. Our experimental results demonstrate that the proposed algorithm is very effective in saving power consumption of circuits significantly.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.2
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• pp.124-130
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• 2005

In this paper, low-power design and implementation techniques for DWT(Discrete Wavelet Transform) of the JPEG2000 compression are proposed. In DWT block of the JPEG2000, linear phase 9 tap and 7 tap filters are used. For low-power implementation of those filters, processor technique for DA(Distributed Arithmetic) filter and minimization technique for number of addition in CSD(Canonic Signed Digit) filter are utilized. Proposed filter structure consists of 3 blocks. In the first CSD coefficient block, every possible 4 bit CSD coefficients are calculated and stored. In second processor block, multiplication is done by MUX and addition processor in terms of the binary values of filter coefficient. Finally, in third block, multiplied values are output and stored in flip-flop train. For comparison of the implementation area and power dissipation, proposed and conventional structures are implemented by using Verilog-HDL coding. In simulation, it is shown that 53.1% of the implementation area can be reduced comparison with those of the conventional structure.