• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.9
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• pp.54-61
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• 2016

A 6-Gbps single-ended receiver with a linear equalizer and a self-reference generator is proposed for a high-speed interface with the double data rate. The proposed single-ended receiver uses a common gate amplifier to increase a voltage gain for an input signal with low voltage level. The continuous-time linear equalizer which reduces gain to the low frequencies and achieves high-frequency peaking gain is implemented in the common gate amplifier. Furthermore, a self-reference generator, which is controlled with the resolution 2.1 mV using digital averaging method, is implemented to maximize the voltage margin by removing the offset noise of the common gate amplifier. The proposed single-ended receiver is designed using a 65-nm CMOS process with 1.2-V supply and consumes the power of 15 mW at the data rate of 6 Gbps. The peaking gain in the frequency of 3 GHz of the designed equalizer is more than 5 dB compared to that in the low frequency.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.10
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• pp.5105-5114
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• 2013

This paper is conducted a research of the cable and filter design considering the deep sea floor environment. The electric architecture which is being used in the subsea plant is comprised of the power supply unit of the high voltage, high-capacity drive system, long cable, and electric motor in the sea area. Conducted emission is occurred by the rapid voltage change at the moment of switching at high speed of inverter for driving motors. The more the length of the cable is lengthened, the worse the motor is influenced by transient voltage. Thus, the over voltage occurred in the drive motor was confirmed by designed wire which is considered R, L, line-to-line C, line-to-gnd C of long cable used in the subsea plant. A guide line of the subsea plant model is also suggested by using a filter to reduce conducted noise of PWM inverter drive-system.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.64-69
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• 2013

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two-step single-slope A/D converter is proposed. The A/D converter is composed of both a 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D converter. In order to have a small noise characteristics, further, a Digital Correlated Double Sampling(D-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA($320{\times}240$) resolution. The fabricated chip size is $5mm{\times}3mm$, and the power consumption is about 35mW at 3.3V supply voltage. The measured conversion speed is 10us, and the frame rate is 220 frames/s.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.14 no.4
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• pp.1-7
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• 2000

In this paper, we study a cause of malfunction of switch to control drive motor in DFMS(Digital Flux Mapping System) which can measure incore neutron flux of the nuclear plant, and develope a method to solve this problem. DFMS has the type of generating contact signal by mechanical switch lever, which is operated whenever thimble detector inserted or withdrawed through thimble Guide Tube. However the characteristics of the lever tend to be changed by mechanical degrade or bad environment and the lever finally generates errotic contact signal. Therefore we installed electric coil ass'yin the outside of Guide Tube instead of mechanical switch assy's. In addition we applied resonance effect to control circuit and installed condenser in the input of power supply to protect noise and interference. After completion of this improvement, we tested this improved device repetitively under the various conditions. In conclusion, we identified the generation of the desired contact signal and the prevention of detector failure through plant surveillance test during normal plant operation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.98-107
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• 2013

This work describes a 13b 100 MS/s 0.13 um CMOS four-stage pipeline ADC for 3G communication systems. The proposed SHA-free ADC employs a range-scaling technique based on switched-capacitor circuits to properly handle a wide input range of $2V_{P-P}$ using a single on-chip reference of $1V_{P-P}$. The proposed range scaling makes the reference buffers keep a sufficient voltage headroom and doubles the offset tolerance of a latched comparator in the flash ADC1 with a doubled input range. A two-step reference selection technique in the back-end 5b flash ADC reduces both power dissipation and chip area by 50%. The prototype ADC in a 0.13 um CMOS demonstrates the measured differential and integral nonlinearities within 0.57 LSB and 0.99 LSB, respectively. The ADC shows a maximum signal-to-noise-and-distortion ratio of 64.6 dB and a maximum spurious-free dynamic range of 74.0 dB at 100 MS/s, respectively. The ADC with an active die area of 1.2 $mm^2$ consumes 145.6 mW including high-speed reference buffers and 91 mW excluding buffers at 100 MS/s and a 1.3 V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.8
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• pp.598-609
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• 2003

This paper describes a CMOS IF PLL frequency synthesizer. The designed frequency synthesizer can be programmed to operate at various intermediate frequencies using different external LC-tanks. The VCO with automatic amplitude control provides constant output power independent of the Q-factor of the external LC-tank. The designed frequency divider includes an 8/9 or 16/17 dual-modulus prescaler and can be programmed to operate at different frequencies by external serial data for various applications. The designed circuit is fabricated using a 0.35${\mu}{\textrm}{m}$ n-well CMOS process. Measurement results show that the phase noise is 114dBc/Hz@100kHz and the lock time is less than 300$mutextrm{s}$. It consumes 16mW from 3V supply. The die area is 730${\mu}{\textrm}{m}$$\times$950${\mu}{\textrm}{m}$.

• Journal of the Korean Solar Energy Society
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• v.29 no.1
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• pp.32-37
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• 2009

Photovoltaic(PV) permits the on-site production of electricity without concern for fuel supply or environmental adverse effects. The electrical power is produced without noise and little depletion of resources. So BIPV(Building-Integrated Photovoltaic) system have been increased around the world. Hereby the relative installation costs of the system will be relatively low compared to traditional installations of PV in high-rise buildings. This paper examined possibility of building integrated balcony PV system and analyzed both performance and problems of this system. The system is influenced by conditions such as irradiation, module temperature, shade and architectural component etc. If this BIPV system of 1.1kW is possible the natural ventilation in the summer case, the temperature of PV module decrease and then the efficiency of PV system increase generally. By the results, the annual averaged PR of BIPV system of cold facade type is about 74.7%.

• Journal of Korea Water Resources Association
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• v.54 no.spc1
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• pp.1083-1093
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• 2021

It is an essential to predict water usage for establishing an optimal supply operation plan and reducing power consumption. However, the water usage by consumer has a non-linear characteristics due to various factors such as user type, usage pattern, and weather condition. Therefore, in order to predict the water consumption, we proposed the methodology linking various techniques that can consider non-linear characteristics of water use and we called it as KWD framework. Say, K-means (K) cluster analysis was performed to classify similar patterns according to usage of each individual consumer; then Wavelet (W) transform was applied to derive main periodic pattern of the usage by removing noise components; also, Deep (D) learning algorithm was used for trying to do learning of non-linear characteristics of water usage. The performance of a proposed framework or model was analyzed by comparing with the ARMA model, which is a linear time series model. As a result, the proposed model showed the correlation of 92% and ARMA model showed about 39%. Therefore, we had known that the performance of the proposed model was better than a linear time series model and KWD framework could be used for other nonlinear time series which has similar pattern with water usage. Therefore, if the KWD framework is used, it will be possible to accurately predict water usage and establish an optimal supply plan every the various event.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.89-94
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• 2008

In this paper, a cascade of a wideband amplifier and a high-Q bandpass filter (BPF) has been realized in a 0.18mm CMOS technology for the applications of subsampling direct-conversion receivers. The wideband amplifier is designed to obtain the -3dB bandwidth of 5.4GHz, and the high-Q BPF is designed to select a 2.4GHz RF signal for the Bluetooth specifications. The measured results demonstrate 18.8dB power gain at 2.34GHz with 31MHz bandwidth, corresponding to the quality factor of 75. Also, it shows the noise figure (NF) of 8.6dB, and the broadband input matching (S11) of less than -12dB within the bandwidth. The whole chip dissipates 64.8mW from a single 1.8V supply and occupies the area of $1.0{\times}1.0mm2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.40-49
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• 2008

A Frequency synthesizer for mobile-DTV applications is implemented using $0.18{\mu}m$ CMOS process with 1.8V supply. PMOS transistors are chosen for VCO core to reduce phase noise. The measurement result of VCO frequency range is 800MHz-1.67GHz using switchable inductors, capacitors and varactors. We use varactor bias technique for the improvement of VCO gain linearity, and the number of varactor biasing are minimized as two. VCO gain deterioration is also improved by using the varactor switching technique. The VCO gain and interval of VCO gain are maintained as low and improved using the VCO frequency calibration block. The sigma-delta modulator for fractional divider is designed by the co-simualtion method for accuracy and efficiency improvement. The VCO, PFD, CP and LF are verified by Cadence Spectre, and the sigma-delta modulator is simulated using Matlab Simulink, ModelSim and HSPICE. The power consumption of the frequency synthesizer is 18mW, and the VCO has 52.1% tuning range according to the VCO maximum output frequency. The VCO phase noise is lower than -100dBc/Hz at 1MHz at 1MHz offset for 1GHz, 1.5GHz, and 2GHz output frequencies.