• Title/Summary/Keyword: Power supply noise

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A Study of Phase Noise Due to Power Supply Noise in a CMOS Ring Oscillator

  • Park Se-Hoon
    • Journal of information and communication convergence engineering
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    • v.3 no.4
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    • pp.184-186
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    • 2005
  • The effect of power supply noise on the phase noise of a ring oscillator is studied. The power supply noise source in series with DC power supply voltage is applied to a 3 stage CMOS ring oscillator. The phase noise due to the power supply noise is modeled by the narrow band phase modulation. The model is verified by the fact that the spectrum of output of ring oscillator has two side bands at the frequencies offset from the frequency of the ring oscillator by the frequency of the power supply noise source. Simulations at several different frequency of the power supply noise reveals that the ring oscillator acts as a low pass filter to the power supply noise. This study, as a result, shows that the phase noise generated by the power supply noise is inversely proportional to the frequency offset from the carrier frequency.

A Study on Phase-Noise and Jitter due to the Power Supply Noise of the CMOS Ring Oscillator (CMOS 링발진기의 전원 잡음에 의한 위상잡음과 Jitter 연구)

  • Park Se-Hoon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.2
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    • pp.298-302
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    • 2006
  • Models for the phase noise and jitter of the ring oscillator with the power supply noise are suggested and verified by simulations. The power supply noise is converted into the phase-noise by the narrow band phase modulation. The phase-noise appears as sideband frequencies apart from the center frequency of the ring oscillator as much as the frequency of the power supply noise. A jitter model describing the linear relation of jitter with the amplitude of the power supply noise is suggested and verified by simulation.

Comparison of ERG Denoising Performance according to Mother Function of Wavelet Transforms (웨이브렛 변환의 모함수에 따른 ERG의 잡음제거 성능 비교)

  • Seo, Jung-Ick;Park, Eun-Kyoo;Jang, Jun-Young
    • Journal of Korean Clinical Health Science
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    • v.4 no.4
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    • pp.756-761
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    • 2016
  • Purpose. Noise occurs at measuring Electoretinogram(ERG) signals as the other bio-signal measurement. It is compared the denoising performance according to the mother function of wavelet transforms. Methods. The ERG signal that generated power supply noise and white noise was used as a sampling signal. The noise of ERG signal was filtered by using haar, db7, bior mother function. The filtering performance of each mother functions was compared using Fourier transform spectrum and SNR(signal to noise ratio). Results. In the haar functioin, the result of the Fourier transform spectrum was that the power supply noise is removed and the white noise performance is not good. The SNR was 27.0404. In the db7 function, the results of Fourier transform spectrum was that the power supply noise is removed and the white noise performance is good. The SNR was 35.1729. In the db7 function, the results of Fourier transform spectrum was that the power supply noise is removed and the white noise performance is the bset. The SNR was 35.4445. Conclusions. The db7, bior function was good results in power supply noise and white noise filtered. The bior function is suitable for filtering noise of the ERG signal.

Clock Scheduling and Cell Library Information Utilization for Power Supply Noise Reduction

  • Kim, Yoo-Seong;Han, Sang-Woo;Kim, Ju-Ho
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.9 no.1
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    • pp.29-36
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    • 2009
  • Power supply noise is fundamentally caused by large current peaks. Since large current peaks are induced by simultaneous switching of many circuit elements, power supply noise can be minimized by deliberate clock scheduling which utilizes nonzero clock skew. In this paper, nonzero skew clock scheduling is used to avoid the large peak current and consequently reduce power supply noise. While previous approaches require extra characterization efforts to acquire current waveform of a circuit, we approximate it only with existing cell library information to be easily adapted to conventional design flow. A simulated annealing based algorithm is performed, and the peak current values are estimated for feasible clock schedules found by the algorithm. The clock schedule with the minimum peak current is selected for a solution. Experimental results on ISCAS89 benchmark circuits show that the proposed method can effectively reduce the peak current.

A Study on Noise Reduction for Auxiliary Power Supply of railway Vehicle Using IGBT (IGBT를 이용한 전동차용 보조전원장치의 소음 저감에 관한 연구)

  • 노애숙;김주범;배기훈;최종묵
    • Proceedings of the KSR Conference
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    • 1998.05a
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    • pp.280-286
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    • 1998
  • In recent years, the interest in noise increases gradually and the low noise level becomes one of the important performances in electrical equipment for railway vehicle. In the auxiliary power supply, most of the noise is made by the current ripple of alternating current reactor(ACL) which filters the output voltage. And this current ripple results from the voltage harmonics across the ACL. So the noise can be reduced by eliminating the voltage harmonics across the ACL. This paper shows harmonic eliminating technique which is making gating signals of upper and lower inverter have a phase difference in the 12-step inverter type auxiliary power supply. This technique was proved by testing on the developed 180KVA auxiliary power supply using IGBT.

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Phase-Locked Loop with Leakage and Power/Ground Noise Compensation in 32nm Technology

  • Kim, Kyung-Ki;Kim, Yong-Bin;Lee, Young-Jun
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.7 no.4
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    • pp.241-246
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    • 2007
  • This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9 V power supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440 MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40 $M{\sim}725$ MHz with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5psec and 42.7 psec, respectively.

A Study on High Precision and High Stability Digital Magnet Power Supply Using Second Order Delta-Sigma modulation (2차 델타 시그마 변조기법을 이용한 고 정밀 및 고 안정 디지털 전자석 전원 장치에 관한 연구)

  • Kim, Kum-Su;Jang, Kil-Jin;Kim, Dong-Hee
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.29 no.3
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    • pp.69-80
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    • 2015
  • This paper is writing about developing magnet power supply. It is very important for power supply to obtain output current in high precision and high stability. As a switching noise and a power noise are the cause of disrupting the stability of output current, to remove these at the front end, low pass filter with 300Hz cutoff frequency is designed and placed. And also to minimize switching noise of the current into magnet and to stop abrupt fluctuations, output filter should be designed, when doing this, we design it by considering load has high value inductance. As power supply demands the stability of less than 5ppm, high precision 24bit(300nV/bit) analog digital converter is needed. As resolving power of 24bit(300nV/bit) analog digital converter is high, it is also very important to design the input stage of analog digital converter. To remove input noise, 4th order low pass filter is composed. Due to the limitation of clock, to minimize quantization error between 15bit DPWM and output of ADC having 24bit resolving power, ${\Sigma}-{\Delta}$ modulation is used and bit contracted DPWM is constituted. And before implementing, to maximize efficiency, simulink is used.

Noise Reduction of PDP Module (PDP 모듈의 소음 저감)

  • Choi, Soo-Yong;Lee, Seok-Yeong;Joo, Jae-Man;Kang, Jung-Hun;Oh, Sang-Kyoung
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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    • 2002.11b
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    • pp.204-209
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    • 2002
  • A PDP(Plasma Display Panel) module consists of a discharge panel, a SMPS(Switched Mode Power Supply) for power supply, driving boards for panel control, and a logic board. Driving boards supply high voltage pulses to induce glow discharge in the PDP panel. The electrical pulses excite the circuit elements and subsequently generate acoustic noises. The main sources of the noise in the circuit are the transformer of SMPS and the power MOSFET(Metal Oxide Semiconductor Field Effect Transistor) of driving boards, and the heat sinks often amplify the noise level. The reduction of the acoustic noises was achieved by modifying both the structural and circuit elements. The structural method was executed by the improvement of heat sinks. The optimization of SMPS and condensers was carried out for the circuit elements.

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Design of Magneto-rheological Fluid Based Device (자기유변유체를 이용한 공학 장치의 설계)

  • Kim, Jeong-Hoon;Lee, Chong-Won;Jung, Byung-Bo;Park, Young-Jin;Cao, Guangzhong
    • Proceedings of the KSME Conference
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    • 2001.11a
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    • pp.544-549
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    • 2001
  • The effect of power supply voltage on the performance limits in a laboratory Magneto-rheological fluid based device was identified by experiments. It suggests that the frequency range of motion for control be limited by the voltage attenuation due to the coil inductance and the maximum power supply voltage set for practical use of MRF devices. In this work, the magnetic and electrical characteristics of MRF device are investigated and a design procedure is formulated to achieve the desired performance for a given power supply.

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A Study on Reduction of Conducted-Noise by the Expanded Node of the Forward Converter (포워드 컨버터의 노드확장에 의한 전도성 노이즈 감소에 관한 연구)

  • Yi, Hee-Hoon;Kwon, Young-Ahn
    • The Transactions of the Korean Institute of Electrical Engineers B
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    • v.55 no.7
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    • pp.374-379
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    • 2006
  • The switch mode power supply is a source of EMI with other equipment as well as with its own proper operation because of rapid changes in voltages and currents within a switching converter. The EMI is transmitted in two forms: radiated and conducted. Conducted noise consists of two categories known as the differential mode and the common mode. Common mode noise current is a major source of EMI in the switch mode Power supply. Recently, a current balancing technique has been studied to reduce the common mode noise. This paper investigates the reduction of common mode noise according to a node expansion of the switch mode power supply which is based on a current balancing technique. In this paper, seven PCB patterns of the forward converter are manufactured and experimented.