• Proceedings of the Korean Magnestics Society Conference
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• 2007.05a
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• pp.253.1-253.1
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• 2007

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.51-51
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• 2009

In this paper, we proposed GaN trench Static Induction Transistor(SIT). Because The compound semiconductor had superior thermal characteristics, GaN and SiC power devices is next generation power semiconductor devices. We carried out modeling of GaN SIT with 2-D device and process simulator. As a result of modeling, we obtained 340V breakdown voltage. The channel thickness was 3um and the channel doping concentration is 1e17cm-3. And we carried out thermal characteristics, too.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.12
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• pp.1018-1022
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• 2009

In this paper, we proposed GaN trench Static Induction Transistor(SIT). Because The compound semiconductor had superior thermal characteristics, GaN and SiC power devices is next generation power semiconductor devices. We carried out modeling of GaN SIT with 2-D device and process simulator. As a result of modeling, we obtained 340 V breakdown voltage. The channel thickness was 3 urn and the channel doping concentration is $1e17\;cm^{-3}$. And we carried out thermal characteristics, too.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2168-2180
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• 2014

In this paper, a generalized power loss algorithm for multilevel neutral-point clamped (NPC) PWM inverters is presented, which is applicable to any level number of multilevel inverters. In the case of three-level inverters, the conduction loss depends on the MI (modulation index) and the PF (power factor), and the switching loss depends on a switching frequency, turn-on and turn-off energy. However, in the higher level of inverters than the three-level, the loss of semiconductor devices cannot be analyzed by conventional methods. The modulation depth should be considered in addition, to find the different conducting devices depending on the MI. In a case study, the power loss analysis for the three- and five-level NPC inverters has been performed with the proposed algorithm. The validity of the proposed algorithm is verified by simulation for the three-and five-level NPC inverters and experiment for three-level NPC inverter.

• Journal of the Semiconductor & Display Technology
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• v.12 no.1
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• pp.41-45
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• 2013

IGZO transparent conductive thin films were widely used as transparent electrode of optoelectronic devices. We have studied the optical and electrical properties of IGZO thin films. The IGZO thin films were deposited on the corning 1737 glass by RF magnetron sputtering method. The RF power in sputtering process was varied as 25, 50, 75and 100 W, respectively. All of the thin films transmittance in the visible range was above 85%. XRD analysis showed that amorphous structure of the thin films without any peak. The thin films were electrically characterized by high mobility above $13.4cm^2/V{\cdot}s$, $7.0{\times}10^{19}cm^{-3}$ high carrier concentration and $6{\times}10^{-3}{\Omega}-cm$ low resistivity. By the studies we found that IGZO transparent thin film can be used as transparent electrodes in electronic devices.

• Fire Science and Engineering
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• v.10 no.2
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• pp.28-39
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• 1996

A recently developed electro-thermal simulation methodology is used to analyze the behavior of a PWM(Pulse-Width-Modulated) voltage source inverter which uses IGBT(Insulated Gate Bipolar Transistor) as the switching devices. In the electro-thermal network simulation methdology, the simulator solves for the temperature distribution within the power semiconductor devices(IGBT electro-thermal model), control logic circuitry, the IGBT gate drivers, the thermal network component models for the power silicon chips, package, and heat sinks as well as the current and voltage within the electrical network. The thermal network describes the flow of heat form the chip surface through the package and heat sink and thus determines the evolution of the chip surface temperature used by the power semiconductor device models. The thermal component model for the device silicon chip, packages, and heat sink are developed by discretizing the nonlinear heat diffusion equation and are represented in component from so that the thermal component models for various package and heat sink can be readily connected to on another to form the thermal network.

• Journal of Semiconductor Engineering
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• v.2 no.3
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• pp.142-153
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• 2021

Recent research on synaptic devices has been reviewed from the perspective of hardware-based neuromorphic computing. In addition, the backgrounds of neuromorphic computing and two training methods for hardware-based neuromorphic computing are described in detail. Moreover, two types of memristor- and CMOS-based synaptic devices were compared in terms of both the required performance metrics and low-power applications. Based on a review of recent studies, additional power-scalable synaptic devices such as tunnel field-effect transistors are suggested for a plausible candidate for neuromorphic applications.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.1
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• pp.17-25
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• 2017

Recently, research and application for a power module have been actively studied according to the increasing demand for the production of vehicles, smartphones and semiconductor devices. The power modules based on the transient liquid phase (TLP) technology for bonding of power semiconductor devices have been introduced in this paper. The TLP bonding has been widely used in semiconductor packaging industry due to inhibiting conventional Pb-base solder by the regulation of end of life vehicle (ELV) and restriction of hazardous substances (RoHS). In TLP bonding, the melting temperature of a joint layer becomes higher than bonding temperature and it is cost-effective technology than conventional Ag sintering process. In this paper, a variety of TLP bonding technologies and their characteristics for bonding of power module have been described.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.13-18
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• 2004

전력계통 분야에서는 HVDC 전력변환소, BTB, UPFC 및 SVC의 안정성 향상 및 안정적인 운용을 위한 체계적인 유지보수 및 관리가 필요하다. 특히 전력계통에 접속된 대용량 전력반도체 소자인 사이리스터 밸브는 운전중에 열적, 전기적인 스트레스를 받게 되며, 이로 인해 밸브의 수명이 감소하여 전력계통의 안정적인 운용을 어렵게 만드는 요인이 된다. 따라서 전력계통 운용의 안정성을 확보하기 위해서는 대용량 사이리스터 밸브의 열적, 전기적 스트레스에 따른 수명 변화를 예측하는 열화진단 기법의 개발이 중요하다. 본 고에서는 대용량 사이리스터 소자의 열화진단 기법에 대한 국내외 현황과 현재 연구가 진행중인 열화 진단 기법에 대해 서술하였으며, 1500V급 사이리스터 소자의 가속열화 실험을 통해 소자의 수명을 예측한 결과를 나타내었다.

• Journal of the Semiconductor & Display Technology
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• v.6 no.2 s.19
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• pp.45-48
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• 2007

The proposed method offers an improved DC/DC converter scheme to increase power density. It is based on half-bridge topology with newly introduced pulse-grouping control method, which helps to reduce the transformer size and the volume of semiconductor devices maintaining high efficiency. Test results with 85W(18.5V/4.6A) design shows that the measured efficiency is 93.5% with power density of $36W/in^3$.